參數(shù)資料
型號(hào)： AD5231BRU10-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT 1024POS 16-TSSOP TR
標(biāo)準(zhǔn)包裝： 1,000
接片： 1024
電阻（歐姆）： 10k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 600 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
AD5231
Data Sheet
Rev. D | Page 20 of 28
CODE (Decimal)
100
75
0
1023
256
R
WA
(D
),
R
WB
(D)
;(
%
o
fNo
mi
n
al
R
AB
)
512
768
50
25
RWB
RWA
02739-
043
Figure 44. RWA(D) and RWB(D) vs. Decimal Code
The general equation that determines the programmed output
resistance between W and B is
W
AB
WB
R
D
R
+
×
=
1024
)
(
(1)
where:
D is the decimal equivalent of the data contained in the RDAC
register.
RAB is the nominal resistance between Terminal A and
Terminal B.
RW is the wiper resistance.
For example, the output resistance values in Table 11 are set
for the given RDAC latch codes with VDD = 5 V (applies to
RAB = 10 k digital potentiometers).
Table 11. RWB (D) at Selected Codes for RAB = 10 k
D (DEC)
RWB(D) ()
Output State
1023
10,005
Full scale
512
50,015
Midscale
1
24.7
1 LSB
0
15
Zero scale (wiper contact resistor)
Note that, in the zero-scale condition, a finite wiper resistance
of 15 is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal switches.
Like the mechanical potentiometer that the RDAC replaces, the
AD5231 part is totally symmetrical. The resistance between
Wiper W and Terminal A also produces a digitally controlled
complementary resistance, RWA. Figure 44 shows the symmetrical
programmability of the various terminal connections. When
RWA is used, Terminal B can be left floating or tied to the wiper.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch is
increased in value.
The general transfer equation for this operation is
W
AB
WB
R
D
R
+
×
=
1024
)
(
(2)
For example, the output resistance values in Table 12 are set for
the RDAC latch codes with VDD = 5 V (applies to RAB = 10 k
digital potentiometers).
Table 12. RWA(D) at Selected Codes for RAB= 10 k
D (DEC)
RWA(D) ()
Output State
1023
24.7
Full scale
512
5015
Midscale
1
10005
1 LSB
0
10,015
Zero scale
The typical distribution of RAB from device to device matches
tightly when they are processed in the same batch. When
devices are processed at a different time, device-to-device
matching becomes process-lot dependent and exhibits a 40%
to +20% variation. The change in RAB with temperature has a
600 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer can be configured to generate an
output voltage at the wiper terminal that is proportional to the
input voltages applied to Terminal A and Terminal B. For
example, connecting Terminal A to 5 V and Terminal B to
ground produces an output voltage at the wiper that can be any
value from 0 V to 5 V. Each LSB of voltage is equal to the
voltage applied across Terminals A–B divided by the 2N position
resolution of the potentiometer divider.
Because AD5231 can also be supplied by dual supplies, the
general equation defining the output voltage at VW with respect
to ground for any given input voltages applied to Terminal A
and Terminal B is
B
AB
W
V
D
V
+
×
=
1024
)
(
(3)
Equation 3 assumes that VW is buffered so that the effect of
wiper resistance is minimized. Operation of the digital
potentiometer in divider mode results in more accurate
operation over temperature. Here, the output voltage is
dependent on the ratio of the internal resistors and not the
absolute value; therefore, the drift improves to 15 ppm/°C.
There is no voltage polarity restriction between Terminal A,
Terminal B, and Terminal W as long as the terminal voltage
(VTERM) stays within VSS < VTERM < VDD.
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