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參數(shù)資料
| 型號(hào)： | AD5231BRU10-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 27/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 1024POS 16-TSSOP TR |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 1024 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 600 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5231
Data Sheet
Rev. D | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
13
12
11
10
9
RDY
VDD
A
W
TOP VIEW
(Not to Scale)
AD5231
1
2
3
4
5
6
7
8
CLK
SDI
SDO
VSS
GND
T
O1
B
O2
CS
PR
WP
02739-
005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
O1
Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit
format is 0x310001.
2
CLK
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3
SDI
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
4
SDO
Serial Data Output Pin. Serves readback and daisy-chain functions.
Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock
pulses, depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7).
In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses
depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for
daisy-chaining multiple devices.
Whenever SDO is used, a pull-up resistor in the range of 1 k to 10 k is needed.
5
GND
Ground Pin. Logic ground reference.
6
VSS
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual-supply applications, it must be
able to sink 40 mA for 25 ms when storing data to EEMEM.
7
T
Reserved for factory testing. Connect to VDD or VSS.
8
B
Terminal B of RDAC.
9
W
Wiper Terminal of RDAC. ADDR (RDAC) = 0x0.
10
A
Terminal A of RDAC.
11
VDD
Positive Power Supply Pin.
12
WP
Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and
Instruction 1 and Instruction 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before
returning to WP high. Tie WP to VDD, if not used.
13
PR
Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
14
CS
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
15
RDY
Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR.
16
O2
Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit
format is 0x310002.
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