參數(shù)資料
型號: AD5382BSTZ-5
廠商: Analog Devices Inc
文件頁數(shù): 9/40頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CH 5V 100-LQFP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: Redesign Change 28/Oct/2011
設(shè)計資源: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011)
AD5382 Channel Monitor Function (CN0012)
標準包裝: 1
設(shè)置時間: 8µs
位數(shù): 14
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 單電源
功率耗散(最大): 65mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
輸出數(shù)目和類型: 32 電壓,單極
采樣率(每秒): 125k
Data Sheet
AD5382
Rev. C | Page 17 of 40
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error, and is
expressed in LSB.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2n–1
VOUT(Zero-Scale) = 0 V
Zero-scale error is a measurement of the difference between
VOUT (actual) and VOUT (ideal), expressed in mV. It is mainly
due to offsets in the output amplifier.
Offset Error
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) in the linear region of the transfer
function, expressed in mV. Offset error is measured on the
AD5382-5 with Code 32 loaded into the DAC register, and on
the AD5382-3 with Code 64.
Gain Error
Gain error is specified in the linear region of the output range
between VOUT= 10 mV and VOUT = AVDD – 50 mV. It is the
deviation in slope of the DAC transfer characteristic from the
ideal and is expressed in %FSR with the DAC output unloaded.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code (all 0s to all 1s, and vice versa)
and output change of all other DACs. It is expressed in LSB.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a to full-scale input change,
and is measured from the BUSY rising edge.
Digital-to-Analog Glitch Energy
This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one DAC due to both the digital change and to the
subsequent analog output change at another DAC. The victim
channel is loaded with midscale. DAC-to-DAC crosstalk is
specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
This is a measurement of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
√Hz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/√Hz in a
1 Hz bandwidth at 10 kHz.
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