參數(shù)資料
型號(hào)： AD5392BCPZ-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/44頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 8CHAN 5V 64LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5390/1/2 Redesign Change 16/May/2012
設(shè)計(jì)資源： 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029)
AD5390/91/92 Channel Monitor Function (CN0030)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 單電源
功率耗散（最大）： 35mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： 125k
Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 29 of 44
3-BYTE MODE
The 3-byte mode lets the user update more than one channel in
a write sequence without having to write the device address byte
each time. The device address byte is required only once and
subsequent channel updates require the pointer byte and the
data bytes. In 3-byte mode, the user begins with an address byte
(R/W = 0) after which the DAC acknowledges that it is prepared
to receive data by pulling SDA low. The address byte is followed
by the pointer byte; this addresses the specific channel in the
DAC to be addressed and is also acknowledged by the DAC.
Address Bits A3 to A0 address all channels on the
AD5390/AD5391. Address Bits A2 to A0 address all channels
on the AD5392. Address Bit A3 is a zero on the AD5392. This is
then followed by the two data bytes. REG1 and REG0 determine
the register to be updated.
If a STOP condition is not sent following the data bytes,
another channel can be updated by sending a new pointer
byte followed by the data bytes. This mode requires only three
bytes to be sent to update any channel once the device has
been initially addressed and reduces the software overhead in
updating the AD539x channels. A STOP condition at any time
exits this mode. Figure 35 shows a typical configuration.
REG0
MSB
LSB
REG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
REG0
MSB
LSB
REG1
1
0
A3
A2
A1
A0
1
AD1
AD0
R/W
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
BY
MASTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE FOR CHANNEL N
MSB
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
POINTER BYTE FOR CHANNEL NEXT CHANNEL
DATA FOR CHANNEL N
DATA FOR CHANNEL NEXT CHANNEL
LEAST SIGNIFICANT DATA BYTE
A/B
0
A3
A2
A1
A0
MSB
03773-
024
Figure 35. 3-Byte Mode I2C Write Operation
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