參數(shù)資料
型號(hào)： AD5415YRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/29頁(yè)
文件大?。?/td> 0K
描述： IC DAC DUAL 12BIT MULT 24-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 62
設(shè)置時(shí)間： 120ns
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
Data Sheet
AD5415
Rev. E | Page 23 of 28
80C51/80L51-to-AD5415 Interface
A serial interface between the DAC and the 80C51 is shown in
Figure 46. TxD of the 80C51 drives SCLK of the DAC serial
interface, and RxD drives the serial data line, SDIN. P1.1 is a
bit-programmable pin on the serial port and is used to drive
SYNC. When data is to be transmitted to the switch, P1.1 is
taken low. The 80C51/80L51 only transmits data in 8-bit bytes;
therefore, only eight falling clock edges occur in the transmit
cycle. To load data correctly to the DAC, P1.1 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. Data on RxD is
clocked out of the microcontroller on the rising edge of TxD
and is valid on the falling edge of TxD. As a result, no glue logic
is required between the DAC and microcontroller interface.
P1.1 is taken high following the completion of this cycle. The
80C51 provides the LSB of its SBUF register as the first bit in
the data stream. The DAC input register requires its data with
the MSB as the first bit received. The transmit routine should
take this into account.
SCLK
TxD
80511
SYNC
P1.1
SDIN
RxD
1ADDITIONAL PINS OMITTED FOR CLARITY.
04461-043
AD54151
Figure 46. 80C51/80L51-to-AD5415 Interface
MC68HC11-to-AD5415 Interface
Figure 47 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5415, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To load data
to the DAC, leave PC7 low after the first eight bits are
transferred and perform a second serial write operation to the
DAC. PC7 is taken high at the end of this procedure.
SCLK
SCK
AD54151
SYNC
PC7
SDIN
MOSI
MC68HC111
1ADDITIONAL PINS OMITTED FOR CLARITY.
04461-044
Figure 47. MC68HC11-to-AD5415 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11, and, with SYNC low, the shift register clocks
data out on the rising edges of SCLK.
MICROWIRE-to-AD5415 Interface
Figure 48 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
SCLK
SK
MICROWIRE1
SYNC
CS
SDIN
SO
AD54151
1ADDITIONAL PINS OMITTED FOR CLARITY.
04461-045
Figure 48. MICROWIRE-to-AD5415 Interface
PIC16C6x/7x-to-AD5415 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON); see the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 49 shows the connection diagram.
SCLK
SCK/RC3
PIC16C6x/7x1
SYNC
RA1
SDIN
SDI/RC4
AD54151
1ADDITIONAL PINS OMITTED FOR CLARITY.
04461-046
Figure 49. PIC16C6x/7x-to-AD5415 Interface
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