參數(shù)資料
型號： AD5415YRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 29/29頁
文件大?。?/td> 0K
描述： IC DAC DUAL 12BIT MULT 24-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 62
設(shè)置時間： 120ns
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
產(chǎn)品目錄頁面： 782 (CN2011-ZH PDF)
AD5415
Data Sheet
Rev. E | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5415
TOP VIEW
(Not to Scale)
SDIN
SCLK
GND
VREFA
IOUT1A
IOUT2A
RFBA
R1A
R3A
R2_3A
R2A
CLR
VDD
VREFB
IOUT1B
IOUT2B
RFBB
R1B
R3B
R2_3B
R2B
LDAC
SDO
SYNC
04461-005
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1A
DAC A Current Output.
2
IOUT2A
DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
3
RFBA
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier
output.
4 to 7
R1A, R2A,
R2_3A, R3A
DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum external components.
8
VREFA
DAC A Reference Voltage Input Pin.
9
GND
Ground Pin.
10
LDAC
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge
when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
11
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
12
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.
13
SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin; they are clocked out on the next 16 opposite
clock edges to the active clock edge.
14
SYNC
Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and SDIN buffers, and the input shift register is enabled. Data is loaded into the shift
register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks,
and data is latched into the shift register on the 16th active clock edge.
15
CLR
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user
to enable the hardware CLR pin as a clear to zero scale or midscale as required.
16
VDD
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
17
VREFB
DAC B Reference Voltage Input Pin.
18 to 21
R3B, R2_3B,
R2B, R1B
DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
a minimum of external components.
22
RFBB
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
23
IOUT2B
DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
24
IOUT1B
DAC B Current Output.
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