參數(shù)資料
型號： AD5415YRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/29頁
文件大小： 0K
描述： IC DAC DUAL 12BIT MULT 24-TSSOP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 62
設置時間： 120ns
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 24-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
產(chǎn)品目錄頁面： 782 (CN2011-ZH PDF)
AD5415
Data Sheet
Rev. E | Page 14 of 28
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero scale and full scale and is
normally expressed in LSB or as a percentage of the full-scale
reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum over the operating
temperature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For this DAC, ideal maximum output is
VREF 1 LSB. The gain error of the DAC is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For this device, it is specified with
a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Digital Crosstalk
The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s, or vice
versa) in the input register of the other DAC. It is expressed
in nV-sec.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s, or vice versa) while keeping LDAC high and
then pulsing LDAC low and monitoring the output of the DAC
whose digital code has not changed. The area of the glitch is
expressed in nV-sec.
Channel-to-Channel Isolation
The portion of input signal from a DAC reference input that
appears at the output of another DAC. It is expressed in decibels.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to fifth harmonics.
1
5
4
3
2
V
THD
2
log
20
Intermodulation Distortion (IMD)
The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at sum
and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 ...
Intermodulation terms are those for which m or n is not equal
to 0. The second-order terms include (fa + fb) and (fa fb), and
the third-order terms are (2fa + fb), (2fa fb), (f + 2fa + 2fb), and
(fa 2fb). IMD is defined as
l
fundamenta
the
of
amplitude
rms
products
distortion
diff
and
sum
the
of
sum
rms
IMD
log
20
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
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