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| 型號： | AD5421BREZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 1.8-12V 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時間： | 50µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 625mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP 裸露焊盤 |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5421
Rev. G | Page 21 of 36
THEORY OF OPERATION
The AD5421 is an integrated device designed for use in loop-
powered, 4 mA to 20 mA smart transmitter applications. In a
single chip, the AD5421 provides a 16-bit DAC and current
amplifier for digital control of the loop current, a voltage
regulator to power the entire transmitter, a voltage reference,
fault alert functions, a flexible SPI-compatible serial interface,
gain and offset adjust registers, as well as other features and
functions. The features of the AD5421 are described in the
following sections.
FAULT ALERTS
The AD5421 provides a number of fault alert features. All
faults are signaled to the controller via the FAULT pin and the
fault register. In the case of a loss of communication between
programs the loop current to an alarm value. If the controller
detects that the FAULT pin is set high, it should then read the
fault register to determine the cause of the fault. Note that the
watchdog timer does not reset and restart its condition with an
alarm active. If the auto fault readback is disabled and an SPI
fault occurs, such that the watchdog timer is timed out, the
watchdog timer remains inactive until the status register is
manually read back by the user. Following this readback, the
watchdog timer resumes operation.
SPI Fault
The SPI fault is asserted if there is no valid communication to
any register of the AD5421 for more than a user-defined period.
The user can program the time period using the SPI watchdog
timeout bits of the control register. The SPI fault bit of the fault
register indicates the fault on the SPI bus. Because this fault is
caused by a loss of communication between the controller and
the AD5421, the loop current is also forced to the alarm value.
The direction of the alarm current (downscale or upscale)
is selected via the ALARM_CURRENT_DIRECTION pin.
Connecting this pin to DVDD selects an upscale alarm current
(22.8 mA/24 mA); connecting this pin to COM selects a
downscale alarm current (3.2 mA).
Packet Error Checking
To verify that data has been received correctly in noisy environ-
ments, the AD5421 offers the option of error checking based on
an 8-bit cyclic redundancy check (CRC). Packet error checking
(PEC) is enabled by writing to the AD5421 with a 32-bit serial
frame, where the least significant eight bits are the frame check
sequence (FCS). The device controlling the AD5421 should
generate the 8-bit FCS using the following polynomial:
C(x) = x 8 + x 2 + x + 1
The 8-bit FCS is appended to the end of the data-word, and
32 data bits are sent to the AD5421 before SYNC is taken high.
If the check is valid, the data is accepted. If the check fails, the
FAULT pin is asserted and the PEC bit of the fault register is set.
After the fault register is read, the PEC bit is reset low and the
FAULT pin returns low.
In the case of data readback, if the AD5421 is addressed with a
32-bit frame, it generates the 8-bit frame check sequence and
appends it to the end of the 24-bit data stream to create a 32-bit
data stream.
SDIN
SYNC
SCLK
UPDATE ON SYNC HIGH
MSB
D23
LSB
D0
24-BIT DATA
24-BIT DATA TRANSFER—NO ERROR CHECKING
SDIN
FAULT
SYNC
SCLK
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
FAULT PIN GOES HIGH
IF ERROR CHECK FAILS
MSB
D31
LSB
D8
D7
D0
24-BIT DATA
8-BIT FCS
32-BIT DATA TRANSFER WITH ERROR CHECKING
09128-
049
Figure 41. PEC Timing
Current Loop Fault
The current loop (ILOOP) fault is asserted when the actual loop
current is not within ±0.01% FSR of the programmed loop
current. If the measured loop current is less than the programmed
loop current, the ILOOP Under bit of the fault register is set. If the
measured loop current is greater than the programmed loop
current, the ILOOP Over bit of the fault register is set. The FAULT
pin is set to logic high in either case.
An ILOOP Over condition occurs when the value of the load current
or DVDD) is greater than the loop current that is programmed
to flow in the loop. An ILOOP under condition occurs when there
is insufficient compliance voltage to support the programmed
loop current, caused by excessive load resistance or low loop
supply voltage.
Overtemperature Fault
There are two overtemperature alert bits in the fault register:
Temp 100°C and Temp 140°C. If the die temperature of the
AD5421 exceeds either 100°C or 140°C, the appropriate bit is
set. If the Temp 140°C bit is set in the fault register, the FAULT
pin is set to logic high.
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