參數(shù)資料
型號: AD5422BREZ
廠商: Analog Devices Inc
文件頁數(shù): 16/44頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 1CH 24TSSOP
產(chǎn)品培訓模塊: Power Line Monitoring
Data Converter Fundamentals
DAC Architectures
設計資源: 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065)
Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077)
標準包裝: 62
設置時間: 25µs
位數(shù): 16
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應商設備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極;1 電壓,單極;1 電壓,雙極
采樣率(每秒): 40k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
Data Sheet
AD5412/AD5422
Rev. I | Page 23 of 44
–0.8
–1.0
–0.6
–0.4
0
0.8
–0.2
0.4
0.6
0.2
1.0
10
15
20
25
30
35
40
DNL
E
RRO
R
(
L
S
B)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
06996-
015
Figure 56. Differential Nonlinearity Error vs. AVDD, Internal RSET
–0.010
–0.015
–0.005
0
0.010
0.005
0.020
0.015
0.025
10
15
20
25
30
35
40
T
O
T
AL
UNADJUS
T
E
D
E
RRO
R
(
%
F
S
R)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
06996-
016
Figure 57. Total Unadjusted Error vs. AVDD, External RSET
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
10
15
20
25
30
35
40
T
O
T
AL
UNADJUS
T
E
D
E
RRO
R
(%
F
S
R
)
AVDD (V)
06996-
032
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
Figure 58. Total Unadjusted Error vs. AVDD, Internal RSET
0
0.5
1.0
1.5
2.0
2.5
–40
–20
0
20
40
60
80
H
E
A
D
R
OOM
V
OLTA
GE
(V)
TEMPERATURE (°C)
AVDD = 15V
AVSS = 0V
IOUT = 24mA
RLOAD = 500
06996-
019
Figure 59. Compliance Voltage Headroom vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
100
200
300
400
500
600
OU
T
PU
T
C
URR
E
N
T
(
A
)
TIME (s)
AVDD = 24V
AVSS = 0V
TA = 25°C
RLOAD = 250
06996-
020
Figure 60. Output Current vs. Time on Power-Up
–50
–40
–30
–20
–10
0
10
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
O
UT
P
UT
CURRE
NT
(
A)
TIME (s)
AVDD = 24V
AVSS = 0V
TA = 25°C
RLOAD = 250
06996-
021
Figure 61. Output Current vs. Time on Output Enable
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