AIDD
參數(shù)資料
型號(hào): AD5422BREZ
廠商: Analog Devices Inc
文件頁數(shù): 43/44頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 1CH 24TSSOP
產(chǎn)品培訓(xùn)模塊: Power Line Monitoring
Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065)
Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077)
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 25µs
位數(shù): 16
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極;1 電壓,單極;1 電壓,雙極
采樣率(每秒): 40k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5412/AD5422
Data Sheet
Rev. I | Page 8 of 44
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
AIDD
Outputs unloaded
2.5
3
mA
Outputs disabled
3.4
4
mA
Current output enabled
3.9
4.4
mA
Voltage output enabled
AISS
Outputs unloaded
0.24
0.3
mA
Outputs disabled
0.5
0.6
mA
Current output enabled
1.1
1.4
mA
Voltage output enabled
DICC
1
mA
VIH = DVCC, VIL = GND
Power Dissipation
128
mW
AVDD = 40 V, AVSS = 0 V, outputs unloaded
120
mW
AVDD = +24 V, AVSS = 24 V, outputs
unloaded
1
Temperature range: 40°C to +85°C; typical at +25°C.
2
When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16
3
Guaranteed by design and characterization; not production tested.
4
For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412.
5
The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from 40°C to +85°C.
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, AVSS = 26.4 V to 3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 k, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Voltage Output
Output Voltage Settling Time
25
s
10 V step to ±0.03 % FSR
32
s
20 V step to ±0.03 % FSR
18
s
5 V step to ±0.03 % FSR
8
s
512 LSB step to ±0.03 % FSR (16-Bit LSB)
Slew Rate
0.8
V/s
Power-On Glitch Energy
10
nV-sec
Digital-to-Analog Glitch Energy
10
nV-sec
Glitch Impulse Peak Amplitude
20
mV
Digital Feedthrough
1
nV-sec
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
0.1
LSB p-p
16-bit LSB
Output Noise (100 kHz Bandwidth)
200
V rms
1/f Corner Frequency
1
kHz
Output Noise Spectral Density
150
nV/√Hz
Measured at 10 kHz, midscale output, 10 V range
AC PSRR
75
dB
200 mV 50 Hz/60 Hz sine wave superimposed on power
supply voltage
Current Output
Output Current Settling Time
10
s
16 mA step to 0.1% FSR
40
s
16 mA step to 0.1% FSR, L = 1 mH
AC PSRR
75
dB
200 mV 50 Hz/60 Hz sine wave superimposed on power
supply voltage
1
Guaranteed by characterization, not production tested.
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