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| 型號(hào)： | AD5422BREZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 1CH 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065) Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077) |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 設(shè)置時(shí)間： | 25µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP 裸露焊盤 |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 40k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
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AD5412/AD5422
Data Sheet
Rev. I | Page 34 of 44
DIGITAL POWER SUPPLY
By default, the DVCC pin accepts a power supply of 2.7 V to
5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V
power supply can be output on the DVCC pin for use as a digital
power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DVCC SELECT
pin unconnected. To disable the internal supply, tie DVCC
SELECT to 0 V. DVCC is capable of supplying up to 5 mA of
current (for a load regulation graph, see Figure 10).
EXTERNAL BOOST FUNCTION
The addition of an external boost transistor, as shown in
by reducing the current flowing in the on-chip output transistor
(dividing it by the current gain of the external circuit). A
discrete NPN transistor with a breakdown voltage, BVCEO,
greater than 40 V can be used. The external boost capability
has been developed for users who may wish to use the AD5412/
AD5422 at the extremes of the supply voltage, load current, and
temperature range. The boost transistor can also be used to
reduce the amount of temperature-induced drift in the part.
This minimizes the temperature-induced drift of the on-chip
voltage reference, which improves on drift and linearity.
BOOST
MJD31C
OR
PBSS8110Z
RLOAD
0.022F
1k
AD5412/
AD5422
IOUT
06996-
061
Figure 70. External Boost Configuration
EXTERNAL COMPENSATION CAPACITOR
The voltage output can ordinarily drive capacitive loads of up to
20 nF; if there is a requirement to drive greater capacitive loads,
of up to 1 F, an external compensation capacitor can be con-
nected between the CCOMP and VOUT pins. The addition of the
capacitor keeps the output voltage stable but also reduces the
bandwidth and increases the settling time of the voltage output.
HART COMMUNICATION
pin, into which a HART signal can be coupled. The HART
signal appears on the current output if the output is enabled. To
achieve a 1 mA peak-to-peak current, the signal amplitude at
the CAP2 pin must be 48 mV peak-to-peak. Assuming that the
modem output amplitude is 500 mV peak-to-peak, its output
must be attenuated by 500/48 = 10.42. If this voltage is used, the
current output should meet the HART amplitude specifications.
Figure 71 shows the recommended circuit for attenuating and
coupling in the HART signal.
HART MODEM
OUTPUT
C1
C2
CAP2
AVDD
06996-
051
Figure 71. Coupling HART Signal
In determining the absolute values of the capacitors, ensure that
the FSK output from the modem is passed undistorted. Thus,
the bandwidth presented to the modem output signal must pass
1200 Hz and 2200 Hz frequencies. The recommended values
are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew
rate of the output is necessary to meet the analog rate of change
requirements for HART.
DIGITAL SLEW RATE CONTROL
user to control the rate at which the output voltage or current
changes. With the slew rate control feature disabled, the output
changes at a rate limited by the output drive circuitry and the
attached load. See Figure 64 for current output step and
Figure 38 for voltage output step. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 14. The parameters are set by the SR clock and
SR step bits. SR clock defines the rate at which the digital slew is
updated; SR step defines by how much the output value changes
at each update. Both parameters together define the rate of
change of the output voltage or current. Table 22 and Table 23
outline the range of values for both the SR clock and SR step
parameters. Figure 72 shows the output current changing for
ramp times of 10 ms, 50 ms, and 100 ms.
Table 22. Slew Rate Step Size Options
SR Step
AD5412 Step Size
(LSB)
AD5422 Step
Size (LSB)
000
1/16
1
001
1/8
2
010
1/4
4
011
1/2
8
100
1
16
101
2
32
110
4
64
111
8
128
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| AD5422BREZ-REEL | 功能描述:IC DAC 16BIT 1CH SRL INP 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5424 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5424_1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface |
| AD5424BRU | 制造商:Analog Devices 功能描述:DAC SGL R-2R 8BIT 16TSSOP - Bulk |
| AD5424YCP | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 8-bit 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8-BIT IOUT DAC PARELLED INT/FACE I.C. - Bulk |
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