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| 型號： | AD5422BREZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 1CH 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065) Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077) |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 設(shè)置時(shí)間： | 25µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP 裸露焊盤 |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 40k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
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AD5412/AD5422
Data Sheet
Rev. I | Page 12 of 44
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
12
11
DVCC
FAULT
GND
LATCH
CLEAR
CLEAR SELECT
AVSS
SCLK
SDIN
GND
SDO
20
21
22
23
24
19
18
17
16
15
14
13
–VSENSE
+VSENSE
VOUT
NC
NOTES
1. NC = NO CONNECT
2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE
IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED
PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
IOUT
BOOST
CCOMP
DVCC SELECT
RSET
REFOUT
REFIN
AVDD
AD5412/
AD5422
TOP VIEW
(Not to Scale)
06996-
005
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT
VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT
ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION
IS MADE AT THE AVSS PIN. IT IS RECOMMENDED THAT THE PADDLE BE
THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
PIN 1
INDICATOR
1
NC
2
FAULT
3
GND
4
CLEAR SELECT
5
CLEAR
6
LATCH
7
SCLK
8
SDIN
9
SDO
10
NC
23 DVCC SELECT
24 CCOMP
25 NC
26 IOUT
27 BOOST
28 CAP1
29 CAP2
30 NC
22 NC
21 NC
1
NC
12
G
ND
13
G
ND
15
G
ND
17
RE
F
O
UT
16
R
SET
18
R
E
FIN
19
NC
20
NC
14
A
V
SS
33
+V
SEN
SE
34
–V
SEN
SE
35
NC
36
A
V
DD
37
A
V
SS
38
NC
39
DV
CC
40
NC
32
V
O
UT
31
NC
TOP VIEW
(Not to Scale)
AD5412/AD5422
06996-
006
Figure 5. TSSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
TSSOP
LFCSP
1
14, 37
AVSS
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0 V if the output voltage range is unipolar.
2
39
DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
This pin can also be configured as a 4.5 V LDO output by leaving the DVCC SELECT pin floating.
3
2
FAULT
Fault Alert. This pin is asserted low when an open circuit is detected in current mode or
an overtemperature is detected. Open drain output must be connected to a pull-up resistor.
4, 12
3, 15
GND
These pins must be connected to 0 V.
18
1, 10, 11, 19, 20,
21, 22, 25, 30,
31, 35, 38, 40
NC
No Connection. Do not connect to these pins.
5
4
CLEAR
SELECT
Selects the voltage output clear value, either zero-scale or midscale code (see Table 21).
6
5
CLEAR
Active High Input. Asserting this pin sets the current output to the bottom of the selected
range or sets the voltage output to the user selected value (zero-scale or midscale).
7
6
LATCH
Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register
data into the DAC register, also updating the output.
8
7
SCLK
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds of up to 30 MHz.
9
8
SDIN
Serial Data Input. Data must be valid on the rising edge of SCLK.
10
9
SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4).
11
12, 13
GND
Ground Reference Pin.
13
16
RSET
An external, precision, low drift 15 k current setting resistor can be connected to this
section.
14
17
REFOUT
Internal Reference Voltage Output. REFOUT = 5 V ± 5 mV.
15
18
REFIN
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a
specified performance.
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| AD5422BREZ-REEL | 功能描述:IC DAC 16BIT 1CH SRL INP 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5424 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5424_1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface |
| AD5424BRU | 制造商:Analog Devices 功能描述:DAC SGL R-2R 8BIT 16TSSOP - Bulk |
| AD5424YCP | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 8-bit 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8-BIT IOUT DAC PARELLED INT/FACE I.C. - Bulk |
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