參數(shù)資料
型號： AD5520JSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 23/24頁
文件大小： 0K
描述： IC PPMU SNGL-CH 64-LQFP
標(biāo)準包裝： 1
類型： 每引腳參數(shù)測量單元（PPMU）
應(yīng)用： 自動測試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 775 (CN2011-ZH PDF)
配用： EVAL-AD5520EBZ-ND - BOARD EVAL FOR AD5520
AD5520
Rev. B | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
CLL
63
CLH
62
FIN
61
M
EA
SVOU
T
60
ME
AS
IO
UT
59
RE
FGND
58
ME
AS
O
UT
57
RE
FGND
56
COMP
IN2
55
COMP
IN1
54
COMP
IN0
53
COMP
OUT2
52
COMP
OUT1
51
COMP
OUT0
50
AV
CC_B
49
FOH
47
MEASI5H
46
MEASI4H
45 FOH3
42
MEASI2H
43
FOH2
44
MEASI3H
48
AVEE_B
41
FOH1
40
MEASI1H
39
FOH0
37
MEASIL
36
MEASVH
35
GUARD(NC)
34
MEASVL
33
AVCC_G
38
MEASI0H
2
CPL
3
DVDD
4
CPOH
7
DGND
6
CPCK
5
CPOL
1
CPH
8
CLHDETECT
9
CLLDETECT
10
QM4
12
MOE
13
CS
14
STB
15
AC0
16
AC1
11
QM5
NC = NO CONNECT
17
DGND
18
DV
DD
19
AM2
20
AM1
21
AM0
22
S
T
ANDBY
23
FSEL
24
M
SEL
25
C
PSEL
26
AV
EE
27
AV
CC
28
AGND
29
AV
EE_
G
30
GUARD
31
NC
32
GUARDIN
PIN 1
AD5520
TOP VIEW
(Not to Scale)
03701-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPH
Upper Comparator Threshold Voltage Input, CPH > CPL.
2
CPL
Lower Comparator Threshold Voltage Input, CPL < CPH.
3, 18
DVDD
Digital Supply Voltage.
4
CPOH
Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH.
5
CPOL
Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL.
6
CPCK
Logic Input. Used to initiate comparator sampling and update CPOH and CPOL.
7, 17
DGND
Digital Ground.
8
CLHDETECT
Logic Output. When high, indicates upper clamp active. See the Clamp Function section.
9
CLLDETECT
Logic Output. When high, indicates lower clamp active. See the Clamp Function section.
10
QM4
Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external relay or
switch. See the High Current Ranges section.
11
QM5
Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external relay or
switch. See the High Current Ranges section.
12
MOE
Active Low MEASOUT Enable.
13
CS
Active Low Logic Input. The device is selected when this pin is low. See the Interface section.
14
STB
Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for different
configurations. Rising edge of STB triggers sequence inputs. See the Interface section.
15
AC0
Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors.
See the Force Control Amplifier section.
16
AC1
Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors.
See the Force Control Amplifier section.
19
AM2
Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable standby
mode. See the Current Ranges section.
20
AM1
Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable standby
mode. See the Current Ranges section.
21
AM0
Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable standby
mode. See the Current Ranges section.
22
STANDBY
Logic Input. When high, device is in standby mode of operation. See the Standby Mode section.
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