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參數(shù)資料
| 型號： | AD5520JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PPMU SNGL-CH 64-LQFP |
| 標準包裝： | 1 |
| 類型： | 每引腳參數(shù)測量單元（PPMU） |
| 應用： | 自動測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5520EBZ-ND - BOARD EVAL FOR AD5520 |
AD5520
Rev. B | Page 17 of 24
FORCE CURRENT
In force current mode, the voltage at FIN is now converted to a
current through the following relationship:
Force Current = VFIN/(RSENSE × 16)
Figure 24 shows a simplified diagram of the PMU when in force
current mode. The control loop consists of the force amplifier
with the current sense amplifier making up the feedback path.
In this case, voltage at the DUT is sensed across the voltage
measure amplifier (Gain = 1) and presented at the MEASVOUT
output.
MEASIHx
MEASIL
G= 16
MEASVH
MEASVL
G = 1
FOHx
RS
RDUT
FIN
VMEASIOUT
VMEASVOUT
ME
AS
IOUT
M
E
A
SVOU
T
CLH
CLL
VCLL
VCLH
VFIN
CONDITION
OUTPUT
VCLH > VDUT
VCLL < VDUT
VCLH > VDUT
VCLL > VDUT
VCLH < VDUT
VCLL < VDUT
REFGNDI/V
V
03701-
024
IDUT =
RS
VFIN
IDUT =
RS
VCLH
IDUT =
RS
VCLL
Figure 24. Current Force, Voltage Measure Mode
MEASURE VOLTAGE
A DUT voltage is tested via the voltage measure amplifier by a
window comparator to ensure that CPH and CPL levels are not
exceeded. In addition, the DUT voltage is automatically tested
against the voltage levels at the clamp, and clamp flags are
enabled if the DUT voltage exceeds either of the levels.
SHORT CIRCUIT PROTECTION
The AD5520 is designed to withstand a direct short circuit on
any of the amplifier outputs.
Figure 25 illustrates the transfer function of the current force
mode.
IDUT
RDUT
VCLL
RDUT
VCLH
VDUT
VFIN
03701-025
Figure 25. Current Force Transfer Function
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