AD5570
Rev. C | Page 6 of 24
TIMING CHARACTERISTICS
DAISY-CHAINING AND READBACK
VDD= +12 V ± 5%, VSS = 12 V ± 5% or VDD = +15 V ± 10%, VSS = 15 V ± 10%, VREF = 5 V, REFGND = AGND = DGND = 0 V, RL = 5 kΩ,
CL = 200 pF to AGND; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Unit
Description
fMAX
2
MHz max
SCLK frequency
t1
500
ns min
SCLK cycle time
t2
200
ns min
SCLK high time
t3
200
ns min
SCLK low time
t4
10
ns min
SYNC to SCLK falling edge setup time
t5
35
ns min
Data setup time
t6
0
ns min
Data hold time
t7
45
ns min
SCLK falling edge to SYNC rising edge
t8
45
ns min
Minimum SYNC high time
t9
0
ns min
SYNC rising edge to LDAC falling edge
t10
50
ns min
LDAC pulse width
200
ns max
Data delay on SDO
1 All parameters guaranteed by design and characterization. Not production tested.
2 All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. SDO; RPULLUP = 5 kΩ, CL = 15 pF.
3 With CL = 0 pF, t14 = 100 ns.
SCLK
SYNC
SDIN
DB15 (N)
DB0 (N)
DB15
(N + 1)
DB15
(N + 1)
DB0
(N + 1)
LDAC1
SDO
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t8
t10
t2
t3
t4
t6
t5
t9
t7
t14
03
76
0-
00
3
Figure 3. Daisy-Chaining Timing Diagram