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參數(shù)資料
| 型號： | AD5629RBRUZ-2-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT I2C/SRL 16TSSOP |
| 標準包裝： | 1,000 |
| 系列： | denseDAC |
| 設置時間： | 2.5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 166k |
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AD5629R/AD5669R
Data Sheet
Rev. D | Page 24 of 32
INTERNAL REFERENCE REGISTER
The internal reference is available on all versions. The on-board
reference is off at power-up by default. The on-board reference
can be turned off or on by a user-programmable internal REF
register by setting Bit DB0 high or low (see Table 10). DB1
selects the internal reference value. Command 1000 is reserved
for setting the internal REF register (see Table 8). Table 11
shows how the state of the bits in the input shift register
corresponds to the mode of operation of the device.
POWER-ON RESET
controls the output voltage during power-up. The AD5629R/
AD5669R DAC output powers up to 0 V and the AD5669R-3
DAC output powers up to midscale. The output remains powered
up at this level until a valid write sequence is made to the DAC.
This is useful in applications where it is important to know the
state of the output of the DAC while it is in the process of powering
up. There is also a software executable reset function that resets
the DAC to the power-on reset code. Command 0111 is reserved
for this reset function (see Table 8). Any events on LDAC or
CLR during power-on reset are ignored.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
DAC ADDRESS
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
0
881
9-
05
0
Figure 53. AD5669R Input Register Contents
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C3
C2
C1
C0
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
COMMAND
DAC ADDRESS
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
0
881
9-
05
2
Figure 54. AD5629R Input Register Contents
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