I
參數(shù)資料
型號: AD5629RBRUZ-2-RL7
廠商: Analog Devices Inc
文件頁數(shù): 8/32頁
文件大小: 0K
描述: IC DAC 12BIT I2C/SRL 16TSSOP
標準包裝: 1,000
系列: denseDAC
設置時間: 2.5µs
位數(shù): 12
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 單電源
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: *
采樣率(每秒): 166k
AD5629R/AD5669R
Data Sheet
Rev. D | Page 16 of 32
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
I DD
(m
A
)
VLOGIC (V)
TA = 25°C
VDD =5V
VDD =3V
08
81
9-
13
6
Figure 30. Supply Current vs. Logic Input Voltage
6
5
4
3
2
1
0
–2
8
6
4
2
0
V
OU
T
(V
)
TIME (s)
VDD = 5V
EXT REF = 5V
TA = 25°C
08
81
9-
13
7
Figure 31. Full-Scale Settling Time, 5 V
5.5
4.5
3.5
2.5
1.5
0.5
5.0
4.0
3.0
2.0
1.0
0
–0.5
–0.0010
0.0010
0.0006
0.0002
–0.0002
–0.0006
VO
L
T
A
G
E
(
V)
TIME (s)
VOUTA
VDD
VDD = 5V
EXT REF = 5V
TA = 25°C
08
81
9-
13
8
Figure 32. Power-On Reset to 0 V
5.5
4.5
3.5
2.5
1.5
0.5
5.0
4.0
3.0
2.0
1.0
0
–0.5
–0.0010
0.0010
0.0006
0.0002
–0.0002
–0.0006
VO
L
T
A
G
E
(
V)
TIME (s)
VOUTA
VDD
VDD = 5V
EXT REF = 5V
TA = 25°C
08
81
9-
13
9
Figure 33. Power-On Reset to Midscale
5.5
4.5
3.5
2.5
1.5
0.5
5.0
4.0
3.0
2.0
1.0
0
–0.5
–10
10
5
0
–5
VO
L
T
A
G
E
(
V)
TIME (s)
VOUTA
24TH CLK RISING EDGE
VDD = 5V
EXT REF = 5V
TA = 25°C
08
81
9-
14
0
Figure 34. Exiting Power-Down to Midscale
CH3 10.0mV
B
W
CH4 5.0V
M400ns
A CH4
1.50V
T 17.0%
3
4
T
VDD = 5V
EXT REF = 5V
TA = 25°C
VOUTA
24TH CLK RISING EDGE
08
81
9-
14
1
Figure 35. Digital-to-Analog Glitch Impulse (Negative)
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