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參數資料
| 型號： | AD5737ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 15/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC QUAD 12BIT CUR 64-LFCSP |
| 標準包裝： | 1 |
| 設置時間： | 15µs |
| 位數： | 12 |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 4 |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸出數目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | * |
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AD5737
Data Sheet
Rev. C | Page 22 of 44
THEORY OF OPERATION
The AD5737 is a quad, precision digital-to-current loop converter
designed to meet the requirements of industrial process control
applications. It provides a high precision, fully integrated, low cost,
single-chip solution for generating current loop outputs. The
current ranges available are 0 mA to 20 mA, 4 mA to 20 mA,
and 0 mA to 24 mA. The output configuration is user-selectable
via the DAC control register.
On-chip dynamic power control minimizes package power
dissipation (see the Dynamic Power Control section).
DAC ARCHITECTURE
The DAC core architecture of the AD5737 consists of two
matched DAC sections. A simplified circuit diagram is shown
in Figure 47. The four MSBs of the 12-bit data-word are decoded
to drive 15 switches, E1 to E15. Each switch connects one of
15 matched resistors either to ground or to the reference buffer
output. The remaining eight bits of the data-word drive Switch S0
to Switch S7 of an 8-bit voltage mode R-2R ladder network.
8-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
2R
S0
S1
S7
E1
E2
E15
VOUT
2R
10067-
069
Figure 47. DAC Ladder Structure
The voltage output from the DAC core is converted to a current,
which is then mirrored to the supply rail so that the application
sees only a current source output (see Figure 48). The current
outputs are supplied by VBOOST_x.
12-BIT
DAC
VBOOST_x
R2
T2
T1
R3
IOUT_x
RSET
A1
A2
10067-
071
Figure 48. Voltage-to-Current Conversion Circuitry
Reference Buffers
The AD5737 can operate with either an external or internal
reference. The reference input requires a 5 V reference for
specified performance. This input voltage is then buffered
before it is applied to the DAC.
POWER-ON STATE OF THE AD5737
tristate mode. After a device power-on or a device reset, it is
recommended that the user wait at least 100 s before writing to
the device to allow time for internal calibrations to take place.
SERIAL INTERFACE
The AD5737 is controlled by a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of the serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking (PEC) is enabled, an additional eight
bits must be written to the AD5737, creating a 32-bit serial
interface (see the Packet Error Checking section).
The DAC outputs can be updated in one of two ways: individual
DAC updating or simultaneous updating of all DACs.
Individual DAC Updating
To update an individual DAC, LDAC is held low while data is
clocked into the DAC data register. The addressed DAC output
is updated on the rising edge of SYNC. See Table 3 and Figure 3
for timing information.
Simultaneous Updating of All DACs
To update all DACs simultaneously, LDAC is held high while
data is clocked into the DAC data register. After LDAC is taken
high, only the first write to the DAC data register of each channel
is valid; subsequent writes to the DAC data register are ignored,
although these subsequent writes are returned if a readback is
initiated. All DAC outputs are updated by taking LDAC low
after SYNC is taken high.
IOUT_x
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIERS
LDAC
SDO
SDIN
12-BIT
DAC
VREFIN
SYNC
DAC DATA
REGISTER
OFFSET
AND GAIN
CALIBRATION
DAC INPUT
REGISTER
SCLK
10067-
072
Figure 49. Simplified Serial Interface of the Input Loading Circuitry
for One DAC Channel
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD5737ACPZ-RL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
| AD5737X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity |
| AD573JD | 功能描述:IC ADC 10BIT SAR REG 20-CDIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD573JN | 功能描述:IC ADC 10BIT SAR REGISTER 20-DIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD573JNZ | 功能描述:IC ADC 10BIT SAR REGISTER 20-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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