CURRENT OUTPUT MODE WITH INTERNAL RSET
參數(shù)資料
型號(hào)： AD5737ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/44頁(yè)
文件大?。?/td> 0K
描述： IC DAC QUAD 12BIT CUR 64-LFCSP
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 15µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： *
AD5737
Data Sheet
Rev. C | Page 40 of 44
APPLICATIONS INFORMATION
CURRENT OUTPUT MODE WITH INTERNAL RSET
When using the internal RSET resistor, the current output is
significantly affected by how many other channels using the
internal RSET are enabled and by the dc crosstalk from these
channels. The internal RSET specifications in Table 1 are for all
four channels enabled with the internal RSET selected and
outputting the same code.
For every channel enabled with the internal RSET, the offset error
decreases. For example, with one current output enabled using the
internal RSET, the offset error is 0.075% FSR. This value decreases
proportionally as more current channels are enabled; the offset
error is 0.056% FSR on each of two channels, 0.029% FSR on
each of three channels, and 0.01% FSR on each of four channels.
Similarly, the dc crosstalk when using the internal RSET is propor-
tional to the number of current output channels enabled with the
internal RSET. For example, with the measured channel at 0x8000
and another channel going from zero to full scale, the dc crosstalk
is 0.011% FSR. With two other channels going from zero to full
scale, the dc crosstalk is 0.019% FSR, and with all three other
channels going from zero to full scale, it is 0.025% FSR.
For the full-scale error measurement in Table 1, all channels are
at 0xFFFF. This means that as any channel goes to zero scale, the
full-scale error increases due to the dc crosstalk. For example,
with the measured channel at 0xFFFF and three channels at
zero scale, the full-scale error is 0.025% FSR. Similarly, if only
one channel is enabled with the internal RSET, the full-scale error
is 0.025% FSR + 0.075% FSR = 0.1% FSR.
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the AD5737 over its
full operating temperature range, a precision voltage reference
must be used. Care should be taken with the selection of the
precision voltage reference. The voltage applied to the reference
inputs is used to provide a buffered reference for the DAC cores.
Therefore, any error in the voltage reference is reflected in the
outputs of the AD5737.
Four possible sources of error must be considered when choosing
a voltage reference for high accuracy applications: initial accuracy,
long-term drift, temperature coefficient of the output voltage,
and output voltage noise.
Initial accuracy error on the output voltage of an external ref-
erence can lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with a low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR435, allows a system
designer to trim out system errors by setting the reference
voltage to a voltage other than the nominal. The trim adjust-
ment can be used at any temperature to trim out any error.
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of the reference output voltage affects
INL, DNL, and TUE. A reference with a tight temperature coef-
ficient specification should be chosen to reduce the dependence
of the DAC output voltage on ambient temperature.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise must be considered. Choos-
ing a reference with as low an output noise voltage as practical
for the system resolution required is important. Precision voltage
references such as the ADR435 (XFET design) produce low output
noise in the 0.1 Hz to 10 Hz bandwidth. However, as the circuit
bandwidth increases, filtering the output of the reference may
be required to minimize the output noise.
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, a capacitor
may be required between the IOUT_x pin and the AGND pin to
ensure stability. A 0.01 F capacitor between IOUT_x and AGND
ensures stability of a load of 50 mH. The capacitive component
of the load may cause slower settling, although this may be
masked by the settling time of the AD5737. There is no maxi-
mum capacitance limit for the current output of the AD5737.
Table 37. Recommended Precision Voltage References
Part No.
Initial Accuracy
(mV Maximum)
Long-Term Drift
(ppm Typical)
Temperature Coefficient
(ppm/°C Maximum)
0.1 Hz to 10 Hz Noise
(V p-p Typical)
±2
50
3
2.25
±3
50
3
10
±2
40
3
8
±5
50
9
8
±2.5
15
10
4
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