參數(shù)資料
型號(hào)： AD5737ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/44頁(yè)
文件大小： 0K
描述： IC DAC QUAD 12BIT CUR 64-LFCSP
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 15µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 4 電流，單極
采樣率（每秒）： *
Data Sheet
AD5737
Rev. C | Page 31 of 44
Slew Rate Control Register
This register is used to program the slew rate control for the
selected DAC channel. The slew rate control is enabled/disabled
and programmed on a per-channel basis. See Table 28 and the
Digital Slew Rate Control section for more information.
READBACK OPERATION
Readback mode is invoked by setting the R/W bit = 1 in the serial
input register write. See Table 29 for the bits associated with a read-
back operation. The DUT_AD1 and DUT_AD0 bits, in association
with Bits[RD4:RD0], select the register to be read (see Table 30).
The remaining data bits in the write sequence are don’t care bits.
During the next SPI transfer, the data that appears on the SDO
output contains the data from the previously addressed register
(see Figure 4). This second SPI transfer should be either a request
to read another register on a third data transfer or a no operation
command. The no operation command for DUT Address 00 is
0x1CE000; for other DUT addresses, Bits[D22:D21] are set
accordingly.
Readback Example
To read back the gain register of AD5737 Device 1, Channel A,
implement the following sequence:
1. Write 0xA80000 to the input register to configure Device
Address 1 for read mode with the gain register of Channel A
selected. The data bits, D15 to D0, are don’t care bits.
2. Execute another read command or a no operation com-
mand (0x3CE000). During this command, the data from
the Channel A gain register is clocked out on the SDO line.
Table 28. Programming the Slew Rate Control Register
D15
D14
D13
D12
D11 to D7
D6 to D3
D2 to D0
0
SREN
SR_CLOCK
SR_STEP
1 X = don’t care.
Table 29. Input Shift Register for a Read Operation
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15 to D0
R/W
DUT_AD1
DUT_AD0
RD4
RD3
RD2
RD1
RD0
1 X = don’t care.
Table 30. Read Addresses (Bits[RD4:RD0])
RD4
RD3
RD2
RD1
RD0
Function
0
Read DAC A data register
0
1
Read DAC B data register
0
1
0
Read DAC C data register
0
1
Read DAC D data register
0
1
0
Read DAC A control register
0
1
0
1
Read DAC B control register
0
1
0
Read DAC C control register
0
1
Read DAC D control register
0
1
0
Read DAC A gain register
0
1
0
1
Read DAC B gain register
0
1
0
1
0
Read DAC C gain register
0
1
0
1
Read DAC D gain register
0
1
0
Read DAC A offset register
0
1
0
1
Read DAC B offset register
0
1
0
Read DAC C offset register
0
1
Read DAC D offset register
1
0
Read DAC A clear code register
1
0
1
Read DAC B clear code register
1
0
1
0
Read DAC C clear code register
1
0
1
Read DAC D clear code register
1
0
1
0
Read DAC A slew rate control register
1
0
1
0
1
Read DAC B slew rate control register
1
0
1
0
Read DAC C slew rate control register
1
0
1
Read DAC D slew rate control register
1
0
Read status register
1
0
1
Read main control register
1
0
1
0
Read dc-to-dc control register
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