參數(shù)資料
型號(hào)： AD5737ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/44頁(yè)
文件大小： 0K
描述： IC DAC QUAD 12BIT CUR 64-LFCSP
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 15µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： *
AD5737
Data Sheet
Rev. C | Page 32 of 44
Status Register
The status register is a read-only register. This register contains
any fault information, as a well as a ramp active bit (Bit D9) and
a user toggle bit (Bit D11). When the STATREAD bit in the
main control register is set, the status register contents can be
read back on the SDO pin during every write sequence. Alterna-
tively, if the STATREAD bit is not set, the status register can be
read using the normal readback operation (see the Readback
Operation section).
Table 31. Decoding the Status Register
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DC-DCD DC-DCC DC-DCB DC-DCA User
toggle
PEC
error
Ramp
active
Over
temp
IOUT_D
fault
IOUT_C
fault
IOUT_B
fault
IOUT_A
fault
1 X = don’t care.
Table 32. Status Register Bit Descriptions
Bit Name
Description
DC-DCD
This bit is set if the dc-to-dc converter on Channel D cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its VMAX voltage; in this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for
more information about the operation of this bit under this condition.
DC-DCC
This bit is set if the dc-to-dc converter on Channel C cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its VMAX voltage; in this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for
more information about the operation of this bit under this condition.
DC-DCB
This bit is set if the dc-to-dc converter on Channel B cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its VMAX voltage; in this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for
more information about the operation of this bit under this condition.
DC-DCA
This bit is set if the dc-to-dc converter on Channel A cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its VMAX voltage; in this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for
more information about the operation of this bit under this condition.
User Toggle
User toggle bit. This bit is set or cleared via the software register and can be used to verify data communications, if needed.
PEC Error
Denotes a PEC error on the last data-word received over the SPI interface.
Ramp Active
This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel).
Over Temp
This bit is set if the AD5737 core temperature exceeds approximately 150°C.
IOUT_D Fault
This bit is set if a fault is detected on the IOUT_D pin.
IOUT_C Fault
This bit is set if a fault is detected on the IOUT_C pin.
IOUT_B Fault
This bit is set if a fault is detected on the IOUT_B pin.
IOUT_A Fault
This bit is set if a fault is detected on the IOUT_A pin.
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