參數(shù)資料
型號(hào)： AD5755ACPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/52頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD 64-LFCSP
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
特色產(chǎn)品： AD5755 / AD5755-1 / AD5757 DACs
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 11µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類(lèi)型： 4 電流，4 電壓
采樣率（每秒）： *
其它名稱(chēng)： AD5755ACPZ-REEL7DKR
Data Sheet
AD5755
Rev. C | Page 41 of 52
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge-sensitive input that allows the
output to be cleared to a preprogrammed 16-bit code. This code
is user programmable via a per channel 16-bit clear code register.
For a channel to clear, that channel must be enabled to be
cleared via the CLR_EN bit (see Table 21) in the channel’s DAC
control register. If the channel is not enabled to be cleared, then
the output remains in its current state independent of the
CLEAR pin level.
When the CLEAR signal is returned low, the relevant outputs
remain cleared until a new value is programmed.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5755 offers the option of packet error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5755 should generate an 8-bit frame check
sequence using the polynomial
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 32 bits are sent
to the AD5755 before taking SYNC high. If the AD5755 sees a
32-bit frame, it performs the error check when SYNC goes high.
If the check is valid, the data is written to the selected register.
If the error check fails, the FAULT pin goes low and the PEC
error bit in the status register is set. After reading the status
register, FAULT returns high (assuming there are no other
faults), and the PEC error bit is cleared automatically. It is not
recommended to tie both AD1 and AD0 low as a short low on
SDIN could possibly lead to a zero-scale update for DAC A.
SDIN
SYNC
SCLK
UPDATE ON SYNC HIGH
MSB
D23
LSB
D0
24-BIT DATA
24-BIT DATA TRANSFER—NO ERROR CHECKING
SDIN
FAULT
SYNC
SCLK
UPDATE ON SYNC HIGH
ONLY IF ERROR CHECK PASSED
FAULT PIN GOES LOW
IF ERROR CHECK FAILS
MSB
D31
LSB
D8
D7
D0
24-BIT DATA
8-BIT CRC
32-BIT DATA TRANSFER WITH ERROR CHECKING
07304-
280
Figure 77. PEC Timing
The PEC can be used for both transmit and receive of data
packets. If status readback during a write is enabled, the PEC
values returned during the status readback during a write
operation should be ignored. If status readback during a write is
disabled, the user can still use the normal readback operation to
monitor status register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert
signal if 0x195 has not been written to the software register
within the programmed timeout period. This feature is useful to
ensure that communication has not been lost between the MCU
and the AD5755 and that these datapath lines are working
properly (that is, SDI, SCLK, and SYNC). If 0x195 is not
received by the software register within the timeout period, the
ALERT pin signals a fault condition. The ALERT signal is active
high and can be connected directly to the CLEAR pin to enable
a clear in the event that communication from the MCU is lost.
The watchdog timer is enabled, and the timeout period (5 ms,
10 ms, 100 ms, or 200 ms) is set in the main control register (see
OUTPUT ALERT
The AD5755 is equipped with an ALERT pin. This is an active
high CMOS output. The AD5755 also has an internal watchdog
timer. When enabled, it monitors SPI communications. If 0x195
is not received by the software register within the timeout period,
the ALERT pin goes active.
INTERNAL REFERENCE
The AD5755 contains an integrated 5 V voltage reference with
initial accuracy of ±5 mV maximum and a temperature drift
coefficient of ±10 ppm maximum. The reference voltage
is buffered and externally available for use elsewhere within
the system. REFOUT must be connected to REFIN to use the
internal reference.
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 72, RSET is an internal sense resistor as part
of the voltage-to-current conversion circuitry. The stability of
the output current value over temperature is dependent on the
stability of the value of RSET. As a method of improving the
stability of the output current over temperature, an external
15 k low drift resistor can be connected to the RSET_x pin of the
AD5755 to be used instead of the internal resistor, R1. The
external resistor is selected via the DAC control register (see
Table 1 outlines the performance specifications of the AD5755
with both the internal RSET resistor and an external, 15 k RSET
resistor. Using an external RSET resistor allows for improved
performance over the internal RSET resistor option. The external
RSET resistor specification assumes an ideal resistor; the actual
performance depends on the absolute value and temperature
coefficient of the resistor used. This directly affects the gain error
of the output, and thus the total unadjusted error. To arrive at
the gain/TUE error of the output with a particular external RSET
resistor, add the percentage absolute error of the RSET resistor
相關(guān)PDF資料
PDF描述
VE-B6J-MV-F1 CONVERTER MOD DC/DC 36V 150W
ICS843031AGI-01LFT IC CLK GENERATOR LVPECL 8-TSSOP
VI-J0M-MZ-F3 CONVERTER MOD DC/DC 10V 25W
VE-B6B-MV-F3 CONVERTER MOD DC/DC 95V 150W
VI-J0M-MZ-F1 CONVERTER MOD DC/DC 10V 25W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD5755BCPZ 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:DAC QUAD 16BIT -26.4/33VIN 64LFCSP 制造商:Analog Devices 功能描述:DAC, QUAD, 16BIT, -26.4/33VIN, 64LFCSP 制造商:Analog Devices 功能描述:DAC, QUAD, 16BIT, -26.4/33VIN, 64LFCSP, Resolution (Bits):16bit, Input Channel Type:Serial, Digital IC Case Style:LFCSP, No. of Pins:64, Data Interface:Microwire, QSPI, SPI, Supply Current:8.6mA, Operating Temperature Min:-40C, , RoHS Compliant: Yes
AD5755BCPZ-REEL7 功能描述:IC DAC 16BIT QUAD 64-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD5755BCPZX 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control
AD5757 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control
AD5757_11 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*