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參數(shù)資料
| 型號(hào)： | AD6655BCPZ-1251 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機(jī) |
| 文件頁(yè)數(shù)： | 58/84頁(yè) |
| 文件大小： | 2012K |
| 代理商： | AD6655BCPZ-1251 |
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AD6655
Bit 0—NCO32 Enable
When Bit 0 is set, this bit enables the 32-bit NCO operating at
the frequency programmed into the NCO frequency register.
When Bit 0 is cleared, the NCO is bypassed and shuts down for
power savings.
NCO Frequency (Register 0x11E to Register 0x121)
Register 0x11E, Bits[7:0]—NCO Frequency Value[7:0]
Register 0x11F, Bits[7:0]—NCO Frequency Value[15:8]
Register 0x120, Bits[7:0]—NCO Frequency Value[23:16]
Register 0x121, Bits[7:0]—NCO Frequency Value[31:24]
This 32-bit value is used to program the NCO tuning frequency.
The frequency value to be programmed is given by the
following equation:
f
Mod
NCO_FREQ
2
32
×
=
Rev. 0 | Page 58 of 84
NCO Phase Offset (Register 0x122 and Register 0x123)
Register 0x122, Bits[7:0]—NCO Phase Value[7:0]
Register 0x123, Bits[7:0]—NCO Phase Value[15:8]
The 16-bit value programmed into the NCO phase value register
is loaded into the NCO block each time the NCO is started or
when an NCO SYNC signal is received. This process allows the
NCO to be started with a known nonzero phase.
Use the following equation to calculate the NCO phase offset
value:
NCO
_
PHASE
= 2
16
×
PHASE
/360
where:
NCO_PHASE
is a decimal number equal to the 16-bit binary
number to be programmed at Register 0x122 and Register 0x123.
PHASE
is the desired NCO phase in degrees.
CLK
CLK
f
f
)
,
(
where:
NCO_FREQ
is a 32-bit twos complement number representing
the NCO frequency register.
f
is the desired carrier frequency in hertz (Hz).
f
CLK
is the AD6655 ADC clock rate in hertz (Hz).
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