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參數(shù)資料
| 型號： | AD6655BCPZ-1251 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機 |
| 文件頁數(shù)： | 61/84頁 |
| 文件大?。?/td> | 2012K |
| 代理商： | AD6655BCPZ-1251 |
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AD6655
EVALUATION BOARD
The AD6655 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configura-
tions. The converter can be driven differentially through a double
balun configuration (default) or optionally through the AD8352
differential driver. The ADC can also be driven in a single-ended
fashion. Separate power pins are provided to isolate the DUT
from the
AD8352
drive circuitry. Each input configuration can
be selected by proper connection of various components (see
Figure 85 to Figure 94). Figure 84 shows the typical bench
characterization setup used to evaluate the ac performance of
the AD6655.
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
See Figure 85 to Figure 102 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V 2 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output of the supply is a 2.1 mm inner diameter
circular jack that connects to the PCB at J16. Once on the PC
board, the 6 V supply is fused and conditioned before connection
to six low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
Rev. 0 | Page 61 of 84
External supplies can be used to operate the evaluation board
by removing L1, L3, L4, and L13 to disconnect the voltage
regulators supplied from the switching power supply. This enables
the user to individually bias each section of the board. Use P3
and P4 to connect a different supply for each section. At least
one 1.8 V supply is needed with a 1 A current capability for
AVDD and DVDD; a separate 1.8 V to 3.3 V supply is recom-
mended for DRVDD. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP VDD) with
a 1 A current capability is needed. To operate the evaluation board
using the alternate SPI options, a separate 3.3 V analog supply
(VS) is needed, in addition to the other supplies. The 3.3 V
supply (VS) should have a 1 A current capability, as well. Solder
Jumper SJ35 allows the user to separate AVDD and DVDD,
if desired.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA100A signal generators or the equivalent. Use 1 m long,
shielded, RG-58, 50 Ω coaxial cable for making connections to the
evaluation board. Enter the desired frequency and amplitude for
the ADC. The AD6655 evaluation board from Analog Devices,
Inc., can accept a ~2.8 V p-p or 13 dBm sine wave input for the
clock. When connecting the analog input source, it is recom-
mended that a multipole, narrow-band, band-pass filter with 50 Ω
terminations be used. Band-pass filters of this type are available
from TTE, Allen Avionics, and K&L Microwave, Inc. Connect the
filter directly to the evaluation board, if possible.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard ADC data capture board (HSC-ADC-EVALCZ).
For more information on the ADC data capture boards and their
optional settings, visit
www.analog.com/FIFO
.
0
USB
CONNECTION
AD6655
EVALUATION BOARD
14-BIT
PARALLEL
CMOS
14-BIT
PARALLEL
CMOS
HSC-ADC-EVALCZ
FPGA BASED
DATA
CAPTURE BOARD
PC RUNNING
VISUAL ANALOG
AND SPI
CONTROLLER
SOFTWARE
1.8V
–
+
–
+
A
V
D
G
G
–
+
5.0V
G
A
3.3V
6V DC
2A MAX
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
–
+
G
3.3V
V
–
+
G
3.3V
SPI
SPI
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
CLK
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
AINB
BAND-PASS
FILTER
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
AINA
BAND-PASS
FILTER
Figure 84. Evaluation Board Connection
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| AD6655 | IF Diversity Receiver |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD6655BCPZ-150 | 制造商:Analog Devices 功能描述:IF Diversity Receiver 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6655BCPZ-150 | 制造商:Analog Devices 功能描述:Communication IC |
| AD6655BCPZ-1501 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655BCPZ-80 | 制造商:Analog Devices 功能描述:IF Diversity Receiver 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6655BCPZ-80 | 制造商:Analog Devices 功能描述:Communication IC |
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