參數(shù)資料
型號: AD7612BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 31/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 750KSPS SAR 48LFCSP
標準包裝: 2,500
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 750k
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 230mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
配用: EVAL-AD7612CBZ-ND - BOARD EVALUATION FOR AD7612
AD7612
Data Sheet
Rev. A | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
P
DBUF
P
DRE
F
RE
F
BUF
IN
TE
M
P
AV
DD
IN
+
AG
ND
VEE
VC
C
IN
RE
F
G
ND
RE
F
D
4/
E
X
T
/IN
T
D
5/
IN
VSYN
C
D
6/IN
V
S
C
LK
D7/
RDC/
S
D
IN
OG
N
D
OV
D
DV
DD
DG
ND
D8/
S
DO
UT
D9/
S
DCL
K
D
10
/SYN
C
D1
1/
RDE
RRO
R
AGND
AVDD
AGND
BYTESWAP
OB/2C
SER/PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
IMPULSE
WARP
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D15/SCCS
D14/SCCLK
D13/SCIN
D12/HW/SW
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
AD7612
TOP VIEW
(Not to Scale)
0
626
5-
0
04
NOTES
1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED
PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 3, 42
AGND
P
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
2, 44
AVDD
P
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
4
BYTESWAP
DI
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.
When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6
WARP
Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode
WARP
IMPULSE
Normal
Low
Impulse
Low
High
Warp
High
Low
Normal
High
See the Modes of Operation section for a more detailed description.
7
IMPULSE
Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the
Modes of Operation section for a more detailed description.
8
SER/PAR
DI
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port
and the remaining data bits are high impedance outputs.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the
state of SER/PAR.
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