參數(shù)資料
型號(hào): AD7634BCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 21/32頁
文件大?。?/td> 0K
描述: IC ADC 18BIT DIFF BIPO 48-LFCSP
標(biāo)準(zhǔn)包裝: 2,500
系列: PulSAR®
位數(shù): 18
采樣率(每秒): 670k
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 225mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極;1 個(gè)差分,雙極
AD7634
Data Sheet
Rev. B | Page 28 of 32
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
This method allows the full throughput and the use of a slower
SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize potential
incorrect bit decisions. For the different modes, the use of a slower
SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode,
and 13 MHz in impulse mode, can be used.
SDIN
SDOUT
D0
123
17
18
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK
4
D2
D1
19
20
MODE[1:0] = 3
RD = 0
16
D17
D16
D15
X17
X16
21
X0
X2
X1
X17
X16
X15
Y17
Y16
t31
X*
t32
t16
t33
t34
t37
t35
t36
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
0
640
6-
04
2
Figure 44. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT
D0
123
BUSY
EXT/INT = 1
INVSCLK = 0
CS
SDCLK
17
D1
MODE[1:0] = 3
RD = 0
18
D17
D16
t31
t32
t16
t37
t35
t36
CNVST
X*
t27
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
DATA = SDIN
06
40
6-
0
43
Figure 45. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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