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參數(shù)資料
| 型號： | AD7634BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT DIFF BIPO 48-LFCSP |
| 標準包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 670k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 225mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
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Data Sheet
AD7634
Rev. B | Page 29 of 32
HARDWARE CONFIGURATION
The AD7634 can be configured at any time with the dedicated
hardware pins WARP, IMPULSE, BIPOLAR, TEN, D0/OB/2C,
and PD for parallel mode (MODE[1:0] = 0, 1, or 2) or serial
hardware mode (MODE[1:0] = 3, HW/SW = high). Programming
the AD7634 for mode selection and input range configuration
can be done before or during conversion. Like the RESET input,
the ADC requires at least one acquisition time to settle as indi-
cated in Figure 46. See Table 6 for pin descriptions. Note that
these inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[17:14] used for software configura-
tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7634 is
programmed using the dedicated write-only serial configurable
port (SCP) for conversion mode, input range selection, output
coding, and power-down using the serial configuration register.
See Table 11 for details of each bit in the configuration register.
The SCP can only be used in serial software mode selected with
MODE[1:0] = 3 and HW/SW = low because the port is multi-
plexed on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 47 for timing details. SCIN is clocked into the con-
figuration register MSB first. The configuration register is an
internal shift register that begins with Bit 8, the START bit. The
9th SCCLK edge updates the register and allows the new settings to
be used. As indicated in the timing diagram, at least one acquisition
time is required from the 9th SCCLK edge. Bits [1:0] are reserved
bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it
is recommended to write to while the AD7634 is not busy con-
verting, as detailed in Figure 47. In this mode, the full 670 kSPS
is not attainable because the time required for SCP access is
(t31 + 9 × 1/ SCCLK + t8) minimum. If the full throughput is
required, the SCP can be written to during conversion; however
it is not recommended to write to the SCP during the last 600 ns
of conversion (BUSY = high) or performance degradation can
result. In addition, the SCP can be accessed in both serial master
and serial slave read during and read after convert modes.
Note that at power up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), thus placing the configuration to 0 V to 5 V input, normal
mode, and twos complemented output.
Table 11. Configuration Register Description
Bit
Name
Description
8
START
START bit. With the SCP enabled (SCCS =
low), when START is high, the first rising edge
of SCCLK (INVSCLK = low) begins to load the
register with the new configuration.
7
BIPOLAR
Input Range Select. Used in conjunction with
Bit 6, TEN, per the following:
Input Range
BIPOLAR
TEN
0 V to 5 V
Low
0 V to 10 V
Low
High
±5 V
High
Low
±10 V
High
6
TEN
Input Range Select. See Bit 7, BIPOLAR.
5
PD
Power Down.
PD = low, normal operation.
PD = high, power down the ADC. The SCP is
accessible while in power-down. To power-up
the ADC, write PD = low on the next configu-
ration setting.
4
IMPULSE
Mode Select. Used in conjunction with Bit 3,
WARP per the following:
Mode
WARP
IMPULSE
Normal
Low
Impulse
Low
High
Warp
High
Low
Normal
High
3
WARP
Mode Select. See Bit 4, IMPULSE.
2
OB/2C
Output Coding
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
1
RSV
Reserved.
0
RSV
Reserved.
WARP,
IMPULSE
BUSY
HW/SW = 1
CNVST
BIPOLAR,
TEN
t8
PD = 0
t8
0
64
06
-0
47
Figure 46. Hardware Configuration Timing
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