參數(shù)資料
型號(hào)： AD7643BCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT DIFF W/REF 48-LFCSP
產(chǎn)品培訓(xùn)模塊： ADC Applications
ADC Architectures
ADC DC/AC Performance
標(biāo)準(zhǔn)包裝： 2,500
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 1.25M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 80mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
配用： EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643
AD7643
Rev. 0 | Page 15 of 28
APPLICATIONS INFORMATION
SW+
COMP
SW–
IN+
REF
REFGND
LSB
MSB
131,072C
65,536C
4C
2C
C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
IN–
4C
2C
C
LSB
MSB
AGND
131,072C 65,536C
0
602
4-
021
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7643 is a very fast, low power, single-supply, precise
18-bit ADC using successive approximation architecture. The
AD7643 is capable of converting 1,250,000 samples per second
(1.25 MSPS).
The AD7643 provides the user with an on-chip, track-and-hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7643 can operate from a single 2.5 V supply and
interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed
in a Pb-free, 48-lead LQFP package or a tiny 48-lead LFCSP
package, which combines space savings with flexibility and
allows the AD7643 to be configured as either a serial or a
parallel interface. The AD7643 is pin-to-pin compatible with
the AD7641 and is a speed upgrade of the AD7674, AD7678,
and AD7679.
CONVERTER OPERATION
The AD7643 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN inputs. A
conversion phase is initiated once the acquisition phase is complete
and the CNVST input goes low. When the conversion phase
begins, SW+ and SW are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the inputs (IN+ and IN) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4
throughVREF/262144). The control logic toggles these switches,
starting with the MSB first, to bring the comparator back into a
balanced condition. After the completion of this process, the
control logic generates the ADC output code and brings BUSY
output low.
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AD7643BSTZ 功能描述:IC ADC 18BIT DIFFER W/REF 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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