參數(shù)資料
型號: AD7650ACPZRL
廠商: Analog Devices Inc
文件頁數(shù): 15/20頁
文件大小: 0K
描述: IC ADC 16BIT CMOS 5V 48LFCSP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 570k
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 77mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個偽差分,單極
配用: EVAL-AD7650CBZ-ND - BOARD EVALUATION FOR AD7650
REV. 0
AD7650
–4–
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 13 AND 14 (continued)
SCLK Last Edge to SYNC Delay
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read After Convert
t28
2.75/3/3.25
s
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay
t29
1/1.25/1.5
s
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t30
50
ns
REFER TO FIGURES 15 AND 16
(Slave Serial Interface Modes)
2
External SCLK Setup Time
t31
5ns
External SCLK Active Edge to SDOUT Delay
t32
316
ns
SDIN Setup Time
t33
5ns
SDIN Hold Time
t34
5ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
NOTES
1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L of 10 pF; otherwise, the load is 60 pF maximum.
3If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
(continued)
IOH
500 A
1.6mA
IOL
TO OUTPUT
PIN
1.4V
CL
60pF*
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V
2V
0.8V
2V
t
DELAY
t
DELAY
Figure 2. Voltage Reference Levels for Timing
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