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參數(shù)資料
| 型號(hào)： | AD7654ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 500KSPS DUAL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 135mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
| 產(chǎn)品目錄頁(yè)面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7654CBZ-ND - BOARD EVALUATION FOR AD7654 |
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AD7654
Rev. B | Page 19 of 28
t1
t3
t4
t17
BUSY
DATA
BUS
t16
NEW A
OR B
PREVIOUS CHANNEL A
OR B
PREVIOUS CHANNEL B
OR NEW A
t10
CS = RD = 0
EOC
CNVST
03
05
7-
02
4
Figure 24. Master Parallel Data Timing for Continuous Read
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase or
during the other channel’s conversion, or during the following
When the data is read during the conversion, however, it is
recommended that it is read only during the first half of the
conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
DATA BUS
t18
t19
BUSY
CURRENT
CONVERSION
CS
RD
03
05
7-
02
5
Figure 25. Slave Parallel Data Timing for a Read After Conversion
PREVIOUS
CONVERSION
t1
t3
t18
t19
t4
BUSY
DATA BUS
t13
t11
t12
t10
CS =0
EOC
CNVST, RD
03
05
7-
02
6
Figure 26. Slave Parallel Data Timing for a Read During Conversion
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 27, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in two bytes on either D[15:8] or D[7:0].
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t18
t19
CS
RD
03
05
7-
02
7
Channel A/B Output
The A/B input controls which channel’s conversion results
(INAx or INBx) are output on the data bus. The functionality
of A/B is detailed in Figure 28. When high, the data from
Channel A is available on the data bus. When low, the data from
Channel B is available on the bus. Note that Channel A can be
read immediately after conversion is done (EOC), while
Channel B is still in its converting phase. However, in any of the
serial reading modes, Channel A data is updated only after
Channel B is converted.
t18
t20
CS
DATA BUS
RD
HI-Z
A/B
HI-Z
CHANNEL A
CHANNEL B
03
05
7-
0
28
Figure 28. A/B Channel Reading
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7654ASTZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
| AD7654ASTZRL | 功能描述:IC ADC 16BIT DUAL 2CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
| AD7655ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:LOW COST 4-CHANNEL 1 MSPS 16-BIT ADC - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LFSCP-48 |
| AD7655ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
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