VBIAS INPUT 12 Input Voltage " />
參數(shù)資料
型號： AD7711ARZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 22/28頁
文件大?。?/td> 0K
描述： IC ADC 24BIT RTD I SOURCE 24SOIC
標準包裝： 400
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 52.5mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 80°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個單端，單極；1 個單端，雙極；1 個差分，單極；1 個差分，雙極
Parameter
A, S Versions
1
Unit
Conditions/Comments
VBIAS INPUT
12
Input Voltage Range
AVDD – 0.85
VREF
See VBIAS Input Section
or AVDD – 3.5
V max
Whichever Is Smaller; +5 V/–5 V or +10 V/0 V
Nominal AVDD/VSS
or AVDD – 2.1
V max
Whichever Is Smaller; +5 V/0 V Nominal AVDD/VSS
VSS + 0.85
VREF
See VBIAS Input Section
or VSS + 3
V min
Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AVDD/VSS
or VSS + 2.1
V min
Whichever Is Greater; +5 V/0 V Nominal AVDD/VSS
VBIAS Rejection
65 to 85
dB typ
Increasing with Gain
LOGIC INPUTS
Input Current
±10
mA max
All Inputs except MCLK IN
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
2.0
V min
MCLK IN Only
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
3.5
V min
LOGIC OUTPUTS
VOL, Output Low Voltage
0.4
V max
ISINK = 1.6 mA
VOH, Output High Voltage
4.0
V min
ISOURCE = 100
mA
Floating State Leakage Current
±10
mA max
Floating State Output Capacitance
13
9
pF typ
TRANSDUCER BURNOUT
Current
4.5
mA nom
Initial Tolerance @ 25
∞C
±10
% typ
Drift
0.1
%/
∞C typ
RTD EXCITATION CURRENTS (RTD1, RTD2)
Output Current
200
mA nom
Initial Tolerance @ 25
∞C
±20
% max
Drift
20
ppm/
∞C typ
Initial Matching @ 25
∞C
±1% max
Matching between RTD1 and RTD2 Currents
Drift Matching
3
ppm/
∞C typ
Matching between RTD1 and RTD2 Current Drift
Line Regulation (AVDD)
200
nA/V max
AVDD = 5 V
Load Regulation
200
nA/V max
Output Compliance
AVDD – 2
V max
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
(1.05
VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (between 1 and 128)
Negative Full-Scale Calibration Limit14
–(1.05
VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (between 1 and 128)
Offset Calibration Limit
15
–(1.05
VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (between 1 and 128)
Input Span
15
0.8
VREF/GAIN
V min
GAIN Is the Selected PGA Gain (between 1 and 128)
(2.1
VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (between 1 and 128)
NOTES
12The AD7711 is tested with the following V
BIAS voltages. With AVDD = 5 V and VSS = 0 V, VBIAS = 2.5 V; with AVDD = 10 V and VSS = 0 V, VBIAS = 5 V, and
with AVDD = 5 V and VSS = –5 V, VBIAS = 0 V.
13Guaranteed by design, not production tested.
14After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.
15These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AV
DD + 30 mV or go more negative than VSS – 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
–3–
REV. G
AD7711
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