TIMING CHARACTERISTICS1, 2 Limit at TMIN
參數(shù)資料
型號: AD7711ARZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大?。?/td> 0K
描述: IC ADC 24BIT RTD I SOURCE 24SOIC
標(biāo)準(zhǔn)包裝: 400
位數(shù): 24
采樣率(每秒): 1.03k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 52.5mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 80°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,單極;1 個單端,雙極;1 個差分,單極;1 個差分,雙極
2
REV.G
AD7711
–5–
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(A, S Versions)
Unit
Conditions/Comments
fCLK IN
4, 5
400
kHz min
Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
10
MHz max
tCLK IN LO
0.4
× t
CLK IN
ns min
Master Clock Input Low Time; tCLK IN = 1/fCLK IN
tCLK IN HI
0.4
× tCLK IN
ns min
Master Clock Input High Time
tr
6
50
ns max
Digital Output Rise Time. Typically 20 ns
tf
6
50
ns max
Digital Output Fall Time. Typically 20 ns
t1
1000
ns min
SYNC Pulse Width
Self-Clocking Mode
t2
0
ns min
DRDY to RFS Setup Time
t3
0
ns min
DRDY to RFS Hold Time
t4
2
× t
CLK IN
ns min
A0 to
RFS Setup Time
t5
0
ns min
A0 to
RFS Hold Time
t6
4
× tCLK IN + 20
ns max
RFS Low to SCLK Falling Edge
t7
7
4
× t
CLK IN + 20
ns max
Data Access Time (
RFS Low to Data Valid)
t8
7
tCLK IN/2
ns min
SCLK Falling Edge to Data Valid Delay
tCLK IN/2 + 30
ns max
t9
tCLK IN/2
ns nom
SCLK High Pulse Width
t10
3
× t
CLK IN/2
ns nom
SCLK Low Pulse Width
t14
50
ns min
A0 to
TFS Setup Time
t15
0
ns min
A0 to
TFS Hold Time
t16
4
× t
CLK IN + 20
ns max
TFS to SCLK Falling Edge Delay Time
t17
4
× tCLK IN
ns min
TFS to SCLK Falling Edge Hold Time
t18
0
ns min
Data Valid to SCLK Setup Time
t19
10
ns min
Data Valid to SCLK Hold Time
NOTES
1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 10 to 13.
3The AD7711 is specified with a 10 MHz clock for AV
DD voltages of 5 V
± 5%. It is specified with an 8 MHz clock for AV
DD voltages greater than 5.25 V and less
than 10.5 V.
4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5The AD7711 is production tested with f
CLK IN at 10 MHz (8 MHz for AVDD > 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6Specified using 10% and 90% points on waveform of interest.
7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
(DVDD = +5 V
5%; AVDD = +5 V or +10 V
3
5%; VSS = 0 V or –5 V
10%; AGND = DGND =
0 V; fCLK IN = 10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.)
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