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參數(shù)資料
| 型號： | AD7712ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SGNL CONDTNR 24SOIC |
| 標準包裝： | 400 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極；1 個差分，雙極 |
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REV. F
AD7712
–23–
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY line, and the write operation does not have any
effect on the status of
DRDY. A write operation to the control
register or the calibration register must always write 24 bits to
the respective register.
Figure 14a shows a write operation to the AD7712 with
TFS
remaining low for the duration of the write operation. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7712
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7712 on the high level of this
SCLK signal with the MSB transferred first. On the last active
high time of SCLK, the LSB is loaded to the AD7712.
Figure 14b shows a timing diagram for a write operation to the
AD7712 with
TFS returning high during the write operation
and returning low again to write the rest of the data word. Tim-
ing parameters and functions are very similar to that outlined
for Figure 14a, but Figure 14b has a number of additional times
to show timing relationships when
TFS returns high in the
middle of transferring a word.
Data to be loaded to the AD7712 must be valid prior to the
rising edge of the SCLK signal.
TFS should return high during
the low time of SCLK. After
TFS returns low again, the next bit
of the data-word to be loaded to the AD7712 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7712.
SCLK (I)
SDATA (I)
TFS (I)
A0 (I)
MSB
LSB
t32
t33
t26
t27
t35
t36
t34
Figure 14a. External Clocking Mode, Control/Calibration Register Write Operation
SCLK (I)
SDATA (I)
TFS (I)
A0 (I)
MSB
BIT N
BIT N+1
t32
t26
t30
t35
t27
t36
t35
t36
Figure 14b. External Clocking Mode, Control/Calibration Register Write Operation
(
TFS Returns High During Write Operation)
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