參數(shù)資料
型號： AD7712ARZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 18/28頁
文件大?。?/td> 0K
描述： IC ADC 24BIT SGNL CONDTNR 24SOIC
標準包裝： 400
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 1
功率耗散（最大）： 45mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個單端，單極；1 個差分，單極；1 個差分，雙極
REV. F
AD7712
–25–
REVERSE
ORDER OF
BITS
START
WRITE DATA FROM
ACCUMULATOR TO
SERIAL BUFFER
BRING
TFS
AND A0 LOW
LOAD DATA FROM
ADDRESS TO
ACCUMULATOR
CONFIGURE AND
INITIALIZE
C/ P
SERIAL PORT
BRING
RFS, TFS
AND A0 HIGH
BRING
TFS
AND A0 HIGH
END
3
Figure 17. Flowchart for Single Write Operation
to the AD7712
AD7712 to 8051 Interface
Figure 18 shows an interface between the AD7712 and the
8XC51 microcontroller. The AD7712 is configured for its
external clocking mode, while the 8XC51 is configured in its
Mode 0 serial interface mode. The
DRDY line from the AD7712
is connected to the Port P1.2 input of the 8XC51, so the
DRDY
line is polled by the 8XC51. The
DRDY line can be connected
to the INT1 input of the 8XC51 if an interrupt driven system is
preferred.
P1.0
P3.0
P3.1
P1.1
P1.2
P1.3
DVDD
8XC51
AD7712
SDATA
A0
RFS
TFS
MODE
DRDY
SYNC
SCLK
Figure 18. AD7712 to 8XC51 Interface
Table VII shows some typical 8XC51 code used for a single
24-bit read from the output register of the AD7712. Table VIII
shows some typical code for a single write operation to the con-
trol register of the AD7712. The 8XC51 outputs the LSB first
in a write operation while the AD7712 expects the MSB first, so
the data to be transmitted has to be rearranged before being
written to the output serial register. Similarly, the AD7712
outputs the MSB first during a read operation while the 8XC51
expects the LSB first. Therefore, the data that is read into the
serial buffer needs to be rearranged before the correct data-word
from the AD7712 is available in the accumulator.
Table VII. 8XC51 Code for Reading from the AD7712
MOV SCON,#00010001B; Configure 8051 for MODE 0
Operation
MOV IE,#00010000B;
Disable All Interrupts
SETB 90H;
Set P1.0, Used as
RFS
SETB 91H;
Set P1.1, Used as
TFS
SETB 93H;
Set P1.3, Used as A0
MOV R1,#003H;
Sets Number of Bytes to Be Read
in A Read Operation
MOV R0,#030H;
Start Address for Where Bytes
Will Be Loaded
MOV R6,#004H;
Use P1.2 as
DRDY
WAIT:
NOP;
MOV A,P1;
Read Port 1
ANL A,R6;
Mask Out All Bits Except
DRDY
JZ READ;
If Zero Read
SJMP WAIT;
Otherwise Keep Polling
READ:
CLR 90H;
Bring
RFS Low
CLR 98H;
Clear Receive Flag
POLL:
JB 98H, READ1
Tests Receive Interrupt Flag
SJMP POLL
READ 1:
MOV A,SBUF;
Read Buffer
RLC A;
Rearrange Data
MOV B.0,C;
Reverse Order of Bits
RLC A; MOV B.1,C; RLC A; MOV B.2,C;
RLC A; MOV B.3,C; RLC A; MOV B.4,C;
RLC A; MOV B.5,C; RLC A; MOV B.6,C;
RLC A; MOV B.7,C;
MOV A,B;
MOV @R0,A;
Write Data to Memory
INC R0;
Increment Memory Location
DEC R1
Decrement Byte Counter
MOV A,R1
JZ END
Jump if Zero
JMP WAIT
Fetch Next Byte
END:
SETB 90H
Bring
RFS High
FIN:
SJMP FIN
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