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參數(shù)資料
| 型號： | AD7712ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SGNL CONDTNR 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極；1 個差分，雙極 |
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REV. F
–12–
AD7712
CIRCUIT DESCRIPTION
The AD7712 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or process
control applications. It contains a sigma-delta (or charge-
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter, and a bidirectional
serial communications port.
The part contains two analog input channels, one programmable
gain differential input, and one programmable gain high level
single-ended input. The gain range on both inputs is from 1 to
128. For the AIN1 input, this means that the input can accept
unipolar signals of between 0 mV and 20 mV and 0 mV and
+2.5 V or bipolar signals in the range from
±20 mV to ±2.5 V
when the reference input voltage equals 2.5 V. The input volt-
age range for the AIN2 input is
±4
VREF/GAIN and is
±10 V
with the nominal reference of 2.5 V and a gain of 1. The input
signal to the selected analog input channel is continuously
sampled at a rate determined by the frequency of the master
clock, MCLK IN, and the selected gain (see Table III). A
chargebalancing A/D converter (sigma-delta modulator) converts
the sampled signal into a digital pulse train whose duty cycle
contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma-
delta modulator with the input sampling frequency being
modified to give the higher gains. A sinc
3 digital low-pass filter
processes the output of the sigma-delta modulator and updates
the output register at a rate determined by the first notch
frequency of this filter. The output data can be read from the
serial port randomly or periodically at any rate up to the output
register update rate. The first notch of this digital filter (and
therefore its –3 dB frequency) can be programmed via an on-chip
control register. The programmable range for this first notch
frequency is from 9.76 Hz to 1.028 kHz, giving a programmable
range for the –3 dB frequency of 2.58 Hz to 269 Hz.
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7712 in the external clocking mode with both
the AVDD and DVDD pins of the AD7712 being driven from the
analog 5 V supply. Some applications will have separate supplies
for both AVDD and DVDD, and in some of these cases, the analog
supply will exceed the 5 V digital supply (see the Power Supplies
and Grounding section).
REF IN(+)
REF OUT
AIN1(+)
AIN1(–)
AIN2
AGND
DGND
MCLK IN
MCLK OUT
MODE
SCLK
SDATA
REF IN(–)
V BIAS
A0
DIFFERENTIAL
ANALOG INPUT
SINGLE-ENDED
ANALOG INPUT
ANALOG
GROUND
DIGITAL
GROUND
DATA
READY
TRANSMIT
(WRITE)
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
ADDRESS
INPUT
5V
AD7712
10 F
0.1 F
ANALOG
5V SUPPLY
AVDD
DVDD
VSS
STANDBY
SYNC
DRDY
TFS
RFS
0.1 F
Figure 3. Basic Connection Diagram
1000
10
0.1
10
1000
10000
100
1
100
NOTCH FREQUENCY – Hz
OUTPUT
NOISE
–
V
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
Figure 2b. Plot of Output Noise vs. Gain and
Notch Frequency (Gains of 16 to 128)
10000
100
0.1
10
1000
10000
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
1000
10
1
100
NOTCH FREQUENCY – Hz
OUTPUT
NOISE
–
V
Figure 2a. Plot of Output Noise vs. Gain and
Notch Frequency (Gains of 1 to 8)
Figures 2a and 2b give information similar to that outlined in Table I. In these plots, the output rms noise is shown for the full range
of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots
are typical values at 25
°C.
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