參數(shù)資料
型號(hào)： AD7712ARZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT SGNL CONDTNR 24SOIC
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 45mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)差分，單極；1 個(gè)差分，雙極
REV. F
AD7712
–15–
Antialias Considerations
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sample frequency (n
19.5 kHz, where
n = 1, 2, 3 . . . ). This means that there are frequency bands,
±f
3 dB wide (f3 dB is cutoff frequency selected by FS0 to FS11),
where noise passes unattenuated to the output. However, due to
the AD7712’s high oversampling ratio, these bands occupy only
a small fraction of the spectrum, and most broadband noise is
filtered. In any case, because of the high oversampling ratio, a
simple, RC, single-pole filter is generally sufficient to attenuate
the signals in these bands on the analog input and thus provide
adequate antialiasing filtering.
If passive components are placed in front of the AIN1 input of the
AD7712, care must be taken to ensure that the source impedance
is low enough so as not to introduce gain errors in the system. The
dc input impedance for the AIN1 input is over 1 G
. The input
appears as a dynamic load that varies with the clock frequency
and with the selected gain (see Figure 7). The input sample
rate, as shown in Table III, determines the time allowed for the
analog input capacitor, CIN, to be charged. External impedances
result in a longer charge time for this capacitor, which may result
in gain errors being introduced on the analog inputs. Table IV
shows the allowable external resistance/capacitance values
such that no gain error to the 16-bit level is introduced, while
Table V shows the allowable external resistance/capacitance
values such that no gain error to the 20-bit level is introduced.
Both inputs of the differential input channels (AIN1) look into
similar input circuitry.
RINT
(7k
TYP)
CINT
(11.5pF TYP)
VBIAS
AIN
SWITCHING FREQUENCY DEPENDS ON
fCLKIN AND SELECTED GAIN
HIGH
IMPEDANCE
>1G
Figure 7. AIN1 Input Impedance
Table IV. Typical External Series Resistance That Will Not
Introduce 16-Bit Gain Error
External Capacitance (pF)
Gain
0
50
100
500
1000
5000
1
184 k
45.3 k 27.1 k 7.3 k 4.1 k 1.1 k
2
88.6 k
22.1 k 13.2 k 3.6 k 2.0 k 560
4
41.4 k
10.6 k 6.3 k
1.7 k
970
270
8–128
17.6 k
4.8 k
2.9 k
790
440
120
Table V. Typical External Series Resistance That Will Not
Introduce 20-Bit Gain Error
External Capacitance (pF)
Gain
0
50
100
500
1000
5000
1
145 k
34.5 k 20.4 k 5.2 k 2.8 k 700
2
70.5 k
16.9 k 10 k
2.5 k
1.4 k 350
4
31.8 k
8.0 k
4.8 k
1.2 k
670
170
8–128
13.4 k
3.6 k
2.2 k
550
300
80
The numbers in Tables IV and V assume a full-scale change on
the analog input. In any case, the error introduced due to longer
charging times is a gain error that can be removed using the
system calibration capabilities of the AD7712 provided that the
resultant span is within the span limits of the system calibration
techniques for the AD7712.
The AIN2 input contains a resistive attenuation network as
outlined in Figure 8. The typical input impedance on this input
is 44 k
. As a result, the AIN2 input should be driven from a
low impedance source.
33k
VBIAS
AIN2
11k
MODULATOR
CIRCUIT
Figure 8. AIN2 Input Impedance
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