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參數(shù)資料
| 型號： | AD7764BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT S/D 312KSPS 28TSSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 312k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 371mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
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AD7764
Rev. A | Page 24 of 32
DAISY CHAINING
Daisy chaining allows numerous devices to use the same digital
interface lines. This feature is especially useful for reducing
component count and wiring connections, such as in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register. When daisy chaining is used, all devices in the
chain must operate in a common power mode and at a common
decimation rate.
The block diagram in Figure 45 shows how to connect devices
to achieve daisy-chain functionality. Figure 45 shows four
AD7764 devices daisy-chained together with a common
MCLK signal applied. This can work in decimate 128× or
decimate 256× mode only.
READING DATA IN DAISY-CHAIN MODE
Referring to Figure 45, note that the SDO line of AD7764 (A)
provides the output data from the chain of AD7764 converters.
Also, note that for the last device in the chain, AD7764 (D), the
SDI pin is connected to ground. All of the devices in the chain
must use common MCLK and SYNC
To enable the daisy-chain conversion process, apply a common
signals.
SYNC
After a
pulse to all devices (see the Synchronization section).
SYNC pulse is applied to all devices, the filter settling
time must pass before the FILTER-SETTLE bit is asserted,
indicating valid conversion data at the output of the chain of
devices. As shown in Figure 46, the first conversion result is
output from the device labeled AD7764 (A). This 32-bit
conversion result is then followed by the conversion results
from the AD7764 (B), AD7764 (C), and AD7764 (D) devices
with all conversion results output in an MSB-first sequence.
The signals output from the daisy chain are the stream of
conversion results from the SDO pin of AD7764 (A) and the
FSO signal output by the first device in the chain, AD7764 (A).
The falling edge of FSO signals the MSB of the first conversion
output in the chain. FSO
The maximum number of devices that can be daisy-chained is
dependent on the decimation rate selected. Calculate the
maximum number of devices that can be daisy-chained by
simply dividing the chosen decimation rate by 32 (the number
of bits that must be clocked out for each conversion).
stays logic low throughout the 32 SCO
clock periods needed to output the AD7764 (A) result and then
goes logic high during the output of the conversion results from
the AD7764 (B), AD7764 (C), and AD7764 (D devices.
provides the maximum number of chained devices for each
decimation rate.
Table 12. Maximum Chain Length for all Decimation Rates
Decimation Rate
Maximum Chain Length
256×
8
128×
4
64×
2
SYNC
SDI
FSI
SDO
MCLK
AD7764
(D)
FSI
SYNC
MCLK
SYNC
SDI
FSI
SDO
MCLK
AD7764
(C)
SYNC
SDI
FSI
SDO
MCLK
AD7764
(B)
SYNC
SDI
FSI
MCLK
AD7764
(A)
SDO
FSO
06518-
018
Figure 45. Daisy Chaining Four Devices in Decimate 128× Mode Using a 40 MHz MCLK Signal
SCO
FSO (A)
32 ×
tSCO
32 ×
tSCO
32 ×
tSCO
32 ×
tSCO
SDO (A)
AD7764 (A)
32-BIT OUTPUT
AD7764 (B)
32-BIT OUTPUT
AD7764 (C)
32-BIT OUTPUT
AD7764 (D)
32-BIT OUTPUT
AD7764 (A)
32-BIT OUTPUT
AD7764 (B)
32-BIT OUTPUT
SDI (A) = SDO (B)
AD7764 (B)
AD7764 (C)
AD7764 (D)
AD7764 (B)
AD7764 (C)
SDI (B) = SDO (C)
AD7764 (C)
AD7764 (D)
AD7764 (C)
AD7764 (D)
SDI (C) = SDO (D)
AD7764 (D)
06518-
019
Figure 46. Daisy-Chain Mode, Data Read Timing Diagram
(for the Daisy-Chain Configuration Shown in Figure 45)
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| AD7764BRUZ-REEL7 | 功能描述:IC ADC 24BIT S/D 312KSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7765 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7765_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 156 kSPS, 112 dB ヒ-ツ ADC with On-Chip Buffers and Serial Interface |
| AD7765BRUZ | 功能描述:IC ADC 24BIT S/D 156KSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7765BRUZ-REEL7 | 功能描述:IC ADC 24BIT S/D 156KSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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