參數(shù)資料
型號(hào): AD7764BRUZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/33頁(yè)
文件大?。?/td> 0K
描述: IC ADC 24BIT S/D 312KSPS 28TSSOP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
采樣率(每秒): 312k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 371mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分,單極;1 個(gè)差分,雙極
產(chǎn)品目錄頁(yè)面: 779 (CN2011-ZH PDF)
AD7764
Rev. A | Page 10 of 32
Pin No.
Mnemonic
Description
14
FSI
Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first
data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details.
15
SYNC
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for further details.
16
RESET/
Reset/Power-Down Pin. When a logic low is sensed on this pin, the part is powered down and all internal
circuitry is reset.
PWRDWN
19
MCLK
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the
frequency of this clock. See the Clocking the AD7764 section for more details.
18
DEC_RATE
Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin,
a decimation rate of 64× is selected. A decimation rate of 128× is selected by leaving the pin floating. A
decimation rate of 256× is selected by setting the pin to ground.
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