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參數(shù)資料
| 型號： | AD7853ANZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24-DIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極；1 個偽差分，雙極 |
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REV. B
–23–
AD7853/AD7853L
SERIAL INTERFACE SUMMARY
Table IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7853/
AD7853L (DOUT Edge) and that the data is latched in on
(DIN Edge). The logic level of the POLARITY pin is shown
and it is clear that this reverses the edges.
In Interface Modes 4 and 5 the
SYNC always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the
SYNC is gated with the
SCLK and the POLARITY pin. Thus the
SYNC may clock out
the MSB of data. Subsequent bits will be clocked out by the
serial clock, SCLK. The conditions for the
SYNC clocking out
the MSB of data is as follows:
With the POLARITY pin high the falling edge of
SYNC will clock
out the MSB if the serial clock is low when the
SYNC goes low.
With the POLARITY pin low the falling edge of
SYNC will clock
out the MSB if the serial clock is high when the
SYNC goes low.
Table IX. SCLK Active Edge for Different Interface Modes
Interface
POLARITY
DOUT
DIN
Mode
Pin
Edge
1, 2, 3
0
SCLK
↑
SCLK
↓
1
SCLK
↓
SCLK
↑
4, 5
0
SCLK
↓
SCLK
↑
1
SCLK
↑
SCLK
↓
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The
SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next
SYNC falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register con-
tents were altered when the interface was lost. Therefore, once
the serial interface is reset, it may be necessary to write the 16-
bit word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC line from a port of the
Controller/DSP to have the
ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7853/AD7853L. It also outlines the various
P/C to which
the particular interface is suited.
The interface mode is determined by the serial mode selection
pins SM1 and SM2. Interface Mode 2 is the default mode. Note
that Interface Mode 1 and 2 have the same combination of SM1
and SM2. Interface Mode 1 may only be set by programming
the control register (see section on control register). External
SCLK and
SYNC signals (SYNC may be hardwired low) are
required for Interfaces Modes 1, 2, and 3. In Interface Modes 4
and 5, the AD7853/AD7853L generates the SCLK and
SYNC.
Some of the more popular
Processors, Controllers, and the
DSP machines that the AD7853/AD7853L will interface to
directly are mentioned here. This does not cover all
Cs, Ps
and DSPs. The interface mode of the AD7853/AD7853L that is
mentioned here for a specific
C, P, or DSP is only a guide
and in most cases another interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
Table X. Interface Mode Description
SM1
SM2
Processor/
Interface
Pin
Controller
Mode
0
8XC51
1 (2-Wire)
8XL51
(DIN is an Input/
PIC17C42
Output pin)
0
68HC11
2 (3-Wire, SPI/QSPI)
68L11
(Default Mode)
0
1
68HC16
3 (QSPI)
PIC16C64
(External Serial
ADSP-21xx
Clock, SCLK, and
DSP56000
External Frame Sync,
DSP56001
SYNC, are required)
DSP56002
DSP56L002
TMS320C30
1
0
68HC16
4 (DSP is Slave)
(AD7853/AD7853L
generates a
noncontinuous
[16 clocks] Serial
Clock, SCLK, and the
Frame Sync,
SYNC)
1
ADSP-21xx
5 (DSP is Slave)
DSP56000
(AD7853/AD7853L
DSP56001
generates a
DSP56002
continuous Serial
DSP56L002
Clock, SCLK, and the
TMS320C20
Frame Sync,
SYNC)
TMS320C25
TMS320C30
TMS320C5x
TMS320LC5x
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7853AR | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk |
| AD7853AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W T/R |
| AD7853ARS | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk |
| AD7853ARS-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Tape and Reel |
| AD7853ARS-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 200KSPS 12-BIT SERL 24SSOP - Tape and Reel |
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