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參數(shù)資料
型號: AD7853ANZ
廠商: Analog Devices Inc
文件頁數(shù): 23/34頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SRL 200KSPS 24-DIP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 15
位數(shù): 12
采樣率(每秒): 200k
數(shù)據(jù)接口: 8051,QSPI?,串行,SPI? µP
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 33mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)偽差分,單極;1 個(gè)偽差分,雙極
Parameter
A Version
1
B Version
1
Units
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH
ISOURCE = 200 A
4
V min
AVDD = DVDD = 4.5 V to 5.5 V
2.4
V min
AVDD = DVDD = 3.0 V to 3.6 V
Output Low Voltage, VOL
0.4
V max
ISINK = 0.8 mA
Floating-State Leakage Current
±10
A max
Floating-State Output Capacitance
4
10
pF max
Output Coding
Straight (Natural) Binary
Unipolar Input Range
Twos Complement
Bipolar Input Range
CONVERSION RATE
Conversion Time
4.6 (18)
s max
(L Versions Only, –40
°C to +85°C, 1 MHz CLKIN)
(10)
s max
(L Versions Only, 0
°C to +70°C, 1.8 MHz CLKIN)
Track/Hold Acquisition Time
0.4 (1)
s min
(L Versions Only)
POWER REQUIREMENTS
AVDD, DVDD
+3.0/+5.5
V min/max
IDD
Normal Mode
5
6 (1.9)
mA max
AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA (1.5);
5.5 (1.9)
mA max
AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Sleep Mode
6
With External Clock On
10
A typ
Full Power-Down. Power Management Bits in Control Register
Set as PMGT1 = 1, PMGT0 = 0
400
A typ
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off
5
A max
Typically 1
A. Full-Power Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 0
200
A typ
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
Normal Mode Power Dissipation
33 (10.5)
mW max
VDD = 5.5 V: Typically 25 mW (8); SLEEP = VDD
20 (6.85)
mW max
VDD = 3.6 V: Typically 15 mW (5.4); SLEEP = VDD
Sleep Mode Power Dissipation
With External Clock On
55
W typ
VDD = 5.5 V; SLEEP = 0 V
36
W typ
VDD = 3.6 V; SLEEP = 0 V
With External Clock Off
27.5
W max
VDD = 5.5 V: Typically 5.5 W; SLEEP = 0 V
18
W max
VDD = 3.6 V: Typically 3.6 W; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.05
× V
REF/–0.05 × VREF
V max/min
Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+1.025
× V
REF/–0.975 × VREF
V max/min
Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A, B Versions, –40
°C to +85°C. For L Versions, A and B Versions f
CLKIN = 1 MHz over –40°C to +85°C temperature range,
B Version fCLKIN = 1.8 MHz over 0°C to +70°C temperature range.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4Sample tested @ +25
°C to ensure compliance.
5All digital inputs @ DGND except for
CONVST, SLEEP, CAL, and SYNC @ DV
DD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST, SLEEP, CAL, and SYNC @ DV
DD. No load on the digital outputs.
Analog inputs @ AGND.
7The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
± 0.05 × V
REF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7853/AD7853L
REV. B
–3–
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