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參數(shù)資料
| 型號： | AD7952BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DIFF 1MSPS 48LFCSP |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 260mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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AD7952
Data Sheet
Rev. A | Page 24 of 32
INTERFACES
DIGITAL INTERFACE
The AD7952 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7952
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using
the OB/2C input pin, both twos complement or straight binary
coding can be used.
Two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7952 in
multicircuit applications and is held low in a single AD7952
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7952. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7952 and
clears the data bus and configuration register. See Figure 35 for
the RESET timing details.
t9
t8
RESET
DATA
BUS
BUSY
CNVST
0
6
589
-03
4
Figure 35. RESET Timing
PARALLEL INTERFACE
The AD7952 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 36 details the timing for this mode.
t1
BUSY
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
CNVST
CS = RD = 0
t10
t4
t11
t3
0658
9-
035
Figure 36. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 37 and
Figure 38, respectively. When the data is read during the conver-
sion, it is recommended that it is read-only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CURRENT
CONVERSION
t13
t12
BUSY
DATA
BUS
RD
CS
06
58
9-
03
6
Figure 37. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t13
t12
t3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t4
t1
06
58
9-
0
37
Figure 38. Slave Parallel Data Timing for Reading (Read During Convert)
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