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參數(shù)資料
| 型號： | AD7952BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/32頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT DIFF 1MSPS 48LFCSP |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 260mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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Data Sheet
AD7952
Rev. A | Page 27 of 32
SLAVE SERIAL INTERFACE
The pins multiplexed on D[19:2] used for slave serial
interface are: EXT/INT, INVSCLK, SDIN, SDOUT,
SDCLK, and RDERROR.
External Clock (SER/PAR = High, EXT/INT = High)
Setting the EXT/INT = high allows the AD7952 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The
external serial clock is gated by CS. When CS and RD are both
low, the data can be read after each conversion or during the
following conversion. A clock can be either normally high or
normally low when inactive. For detailed timing diagrams,
see Figure 43 and Figure 44.
While the AD7952 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result may occur. This is
particularly important during the last 450 ns of the conversion
phase because the AD7952 provides error correction circuitry
that can correct for an improper bit decision made during the
first part of the conversion phase. For this reason, it is recom-
mended that any external clock provided is a discontinuous
clock that transitions only when BUSY is low or, more importantly,
that it does not transition during the last 450 ns of BUSY high.
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 43 shows the detailed timing diagrams for this method.
After a conversion is complete, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 14 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
Also in the read after convert mode, the AD7952 provides a
daisy-chain feature for cascading multiple converters together
using the serial data input pin, SDIN. This feature is useful for
reducing component count and wiring connections when
desired, for instance, in isolated multiconverter applications.
See Figure 43 for the timing details.
An example of the concatenation of two devices is shown in
Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK
falling edge when INVSCLK = low). Therefore, the MSB
of the upstream converter follows the LSB of the downstream
converter on the next SDCLK cycle. In this mode, the 40 MHz
SDCLK rate cannot be used because the SDIN-to-SDCLK setup
time, t33, is less than the minimum time specified. (SDCLK-
to-SDOUT delay, t32, is the same for all converters when
simultaneously sampled). For proper operation, the SDCLK
edge for latching SDIN (or period of SDCLK) needs to be
33
32
SDCLK
t
2
/
1
or the maximum SDCLK frequency needs to be
)
(
2
1
33
32
SDCLK
t
f
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
SDCLK
SDOUT
RDC/SDIN
AD7952
#1
(DOWNSTREAM)
AD7952
#2
(UPSTREAM)
BUSY
OUT
BUSY
DATA
OUT
SDCLK
RDC/SDIN
SDOUT
SDCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
0
65
89
-04
1
Figure 42. Two AD7952 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 44 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 14 clock pulses, and depending on the SDCLK
frequency, can be valid on both the falling and rising edges
of the clock. The 14 bits have to be read before the current
conversion is completed; otherwise, RDERROR is pulsed high
and can be used to interrupt the host interface to prevent
incomplete data reading.
To reduce performance degradation due to digital activity,
a fast discontinuous clock of at least 40 MHz is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase.
The daisy-chain feature should not be used in this mode because
digital activity occurs during the second half of the SAR
conversion phase, likely resulting in performance degradation.
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| AD7952BCPZRL | 功能描述:IC ADC 14BIT DIFF 1MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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