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參數(shù)資料
| 型號： | AD8195ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFF HDMI/DVI W/EQUAL 40LFCSP |
| 標準包裝： | 750 |
| 功能： | 開關(guān) |
| 電路： | 1 x 1:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD8195
Data Sheet
Rev. B | Page 14 of 20
PREEMPHASIS
The preemphasized TMDS outputs precompensate the trans-
mitted signal to account for losses in systems with long cable
runs. These long cable runs selectively attenuate the high
frequency energy of the signal, leading to degraded transition
times and eye closure. Similar to a receive equalizer, the goal of
the preemphasis filter is to boost the high frequency energy in
the signal. However, unlike the receive equalizer, the preemphasis
filter is applied before the channel, thus predistorting the
transmitted signal to account for the loss of the channel. The
series connection of the preemphasis filter and the channel
results in a flatter frequency response than that of the channel,
thus leading to improved high frequency energy, improved
transition times, and improved eye opening on the far end of
the channel. Using a preemphasis filter to compensate for
channel losses allows for longer cable runs with or without a
receiver equalizer on the far end of the channel.
When there is no receive equalizer on the far end of the channel,
the preemphasis filter should allow longer cable runs than
would be acceptable with no preemphasis. When there is both a
preemphasis filter on the near end and a receive equalizer on
the far end of the channel, the allowable cable run should be
longer than either compensation could achieve alone. The pulse
response of a preemphasized waveform is shown in Figure 32.
The output voltage levels and symbol descriptions are listed in
Table 9 and Table 10, respectively. The preemphasis circuit is
designed to work up to 2.25 Gbps and does not perform
suitably at higher data rates.
VOCM
VH
VL
VOSE-BOOST
VTTO
VOSE-DC
<TBIT
VOCM
VTTO
VH
VL
VOSE-DC
PREEMPHASIS OFF
PREEMPHASIS ON
07049-
006
Figure 32. Preemphasis Pulse Response
AUXILIARY LINES
The auxiliary (low speed) lines provide buffering for the DDC
and CEC signals. The auxiliary lines are powered independently
from the TMDS link; therefore, their functionality can be
maintained even when the system is powered off. In an application,
these lines can be powered by connecting AMUXVCC to the
5 V supply provided from the video source through the input
HDMI connector.
DDC Buffers
The DDC buffers are 5 V tolerant bidirectional lines that can
carry extended display identification data (EDID), HDCP
encryption, and other information, depending on the specific
application. The DDC buffers are bidirectional and fully support
arbitration, clock synchronization, clock stretching, slave acknowl-
edgement, and other relevant features of a standard mode I2C bus.
The DDC buffers also have separate voltage references for the
input side and the output side, allowing the sink to use internal
bus voltages (3.3 V), alleviating the need for 5 V tolerant I/Os
for system ASICs. The logic level for the DDC_IN bus is set by
the voltage on VREF_IN, and the logic level for the DDC_OUT
bus is set by the voltage on VREF_OUT. For example, if the
DDC_IN bus is using 5 V I2C, the VREF_IN power supply pin
should be connected to a 5 V power supply. If the DDC_OUT
bus is using 3.3 V I2C, the VREF_OUT power supply pin should
be connected to a 3.3 V power supply.
CEC Buffer
The CEC buffer is a 3.3 V tolerant bidirectional buffer with
integrated pull-up resistors. This buffer enables full compliance
with all CEC specifications, including but not limited to input
capacitance, logic levels, transition times, and leakage (both with
the system power on and off). This allows the CEC functionality
to be implemented in a standard microcontroller that may not
have CEC compliant I/Os. The CEC buffer is powered from the
AMUXVCC supply.
Table 9. Output Voltage Levels
PE Setting
Boost (dB)
IT (mA)
VOSE-DC (mV p-p)
VOSE-BOOST (mV p-p)
VOCM (V)
VH (V)
VL (V)
0
20
500
3.050
3.3
2.8
1
6
40
500
1000
2.8
3.3
2.3
Table 10. Symbol Definitions
Symbol
Formula
Definition
VOSE-DC
IT|PE = 0 × 25
Single-ended output voltage swing after settling
VOSE-BOOST
IT × 25
Boosted single-ended output voltage swing
VOCM (DC-Coupled)
VTTO – IT/2 × 25
Common-mode voltage when the output is dc-coupled
VH
VOCM + VOSE-BOOST/2
High single-ended output voltage excursion
VL
VOCM VOSE-BOOST/2
Low single-ended output voltage excursion
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參數(shù)描述 |
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| AD8195-EVALZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
| AD8195XCPZ | 功能描述:IC BUFF HDMI/DVI W/EQUAL 40LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購買時間 類型:HDMI/DVI 緩沖器 應(yīng)用:HDTV 安裝類型:表面貼裝 封裝/外殼:40-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:40-LFCSP-VQ（6x6） 標準包裝:1 |
| AD8196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2:1 HDMI/DVI Switch with Equalization |
| AD8196ACPZ | 功能描述:IC SWITCH DVI/HDMI 2:1 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD8196ACPZ-R7 | 功能描述:IC SWITCH DVI/HDMI 2:1 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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