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參數(shù)資料
| 型號(hào)： | AD8304ARUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGARITHM CONV 160DB 14-TSSOP |
| 設(shè)計(jì)資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 對(duì)數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. A
–2–
AD8304–SPECIFICATIONS (V
P = 5 V, VN = 0 V, TA = 25 C, unless otherwise noted.)
Parameter
Conditions
Min
1
Typ
Max
1
Unit
INPUT INTERFACE
Pin 4, INPT; Pin 3 and Pin 5, VSUM
Specified Current Range
Flows toward INPT Pin
100
pA
10
mA
Input Node Voltage
Internally preset; may be altered
0.46
0.5
0.54
V
Temperature Drift
–40
°C < TA < +85°C
0.02
mV/
°C
Input Guard Offset Voltage
VIN – VSUM
–20
+20
mV
PHOTODIODE BIAS
2
Established between Pin 6, VPDB, and Pin 4
Minimum Value
IPD = 100 pA
70
100
mV
Transresistance
200
mV/mA
LOGARITHMIC OUTPUT
Pin 8, VLOG
Slope
Laser-trimmed at 25
°C
196
200
204
mV/dec
0
°C < T
A < 70
°C
194
207
mV/dec
Intercept
Laser-trimmed at 25
°C60
100
140
pA
0
°C < TA < 70°C35
175
pA
Law Conformance Error
10 nA < IPD < 1 mA, Peak Error
0.05
0.25
dB
1 nA < IPD < 1 mA, Peak Error
0.1
0.7
dB
Maximum Output Voltage
1.6
V
Minimum Output Voltage
Limited by VN = 0 V
0.1
V
Output Resistance
Laser-trimmed at 25
°C
4.95
5
5.05
k
REFERENCE OUTPUT
Pin 7, VREF
Voltage WRT Ground
Laser-trimmed at 25
°C
1.98
2
2.02
V
–40
°C < TA < +85°C
1.92
2.08
V
Output Resistance
2
OUTPUT BUFFER
Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT
Input Offset Voltage
–20
+20
mV
Input Bias Current
Flowing out of Pin 9 or Pin 13
0.4
A
Incremental Input Resistance
35
M
Output Range
RL = 1 k
to ground
VP – 0.1
V
Output Resistance
0.5
Wide-Band Noise
3
IPD > 1
A (see Typical Performance Characteristics)
1
V/√Hz
Small Signal Bandwidth
3
IPD > 1
A (see Typical Performance Characteristics)
10
MHz
Slew Rate
0.2 V to 4.8 V output swing
15
V/
s
POWER-DOWN INPUT
Pin 2, PWDN
Logic Level, HI State
–40
°C < TA < +85°C, 2.7 V < VP < 5.5 V
2
V
Logic Level, LO State
–40
°C < T
A < +85
°C, 2.7 V < V
P < 5.5 V
1
V
POWER SUPPLY
Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG
Positive Supply Voltage
3.0
5
5.5
V
Quiescent Current
4.5
5.3
mA
In Disabled State
60
A
Negative Supply Voltage4
|1VP –VN| < 8V
0
–5.5
V
NOTES
1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.
3Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics.
4Optional
Specications subject to change without notice.
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