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參數(shù)資料
| 型號(hào)： | AD8304ARUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 0K |
| 描述： | IC LOGARITHM CONV 160DB 14-TSSOP |
| 設(shè)計(jì)資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 對(duì)數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. A
–10–
AD8304
INPUT – A
100p
10m
1n
10n
100n
1
10
100
1m
1.6
V
LOG
–
V
0.8
0
0.4
1.2
Figure 2. Ideal Form of VLOG vs. IPD
Using a value of 0.3 pF for CJ evaluates to 20 MHz/mA. There-
fore, the minimum bandwidth at IPD = 100 pA would be 2 kHz.
While this simple model is useful in making a point, it excludes
other effects that limit its usefulness. For example, the network
R1, C1 in Figure 1, which is necessary to stabilize the system over
the full range of currents, affects bandwidth at all values of IPD.
Later signal processing blocks also limit the maximum value.
TPC 7 shows ac response curves for the AD8304 at eight repre-
sentative currents of 100 pA to 10 mA, using R1 = 750
and
C1 = 1000 pF. The values for R1 and C1 ensure stability over
the full 160 dB dynamic range. More optimal values may be used
for smaller subranges. A certain amount of experimental trial and
error may be necessary to select the optimum input network
component values for a given application.
Turning now to the noise performance of a translinear log amp,
the relationship between IPD and the voltage noise spectral density,
SNSD, associated with the VBE of Q1, evaluates to the following:
S
I
NSD
PD
=
14 7
.
(14)
where SNSD is nV/Hz, IPD is expressed in microamps and TA = 25
°C.
For an input of 1 nA, SNSD evaluates to almost 0.5
V/√Hz; assum-
ing a 20 kHz bandwidth at this current, the integrated noise
voltage is 70
V rms. However, the calculation is not complete.
The basic scaling of the VBE is approximately 3 mV/dB; translated
to 10 mV/dB, the noise predicted by Equation 14 must be multi-
plied by approximately 3.33. The additive noise effects associated
with the reference transistor, Q2, and the temperature compen-
sation circuitry must also be included. The final voltage noise
spectral density presented at the VLOG Pin varies inversely with
IPD, but not as simple as square root. TPCS 8 and 9 show the
measured noise spectral density versus frequency at the VLOG
output, for the same nine-decade spaced values of IPD.
Chip Enable
The AD8304 may be powered down by taking the PWDN Pin
to a high logic level. The residual supply current in the disabled
mode is typically 60
A.
USING THE AD8304
The basic connections (Figure 3) include a 2.5:1 attenuator in
the feedback path around the buffer. This increases the basic slope
of 10 mV/dB at the VLOG Pin to 25 mV/dB at VOUT. For the
full dynamic range of 160 dB (80 dB optical), the output swing
is thus 4.0 V, which can be accommodated by the rail-to-rail
output stage when using the recommended 5 V supply.
The capacitor from VLOG to ground forms an optional single-
pole low-pass filter. Since the resistance at this pin is trimmed
to 5 k
, an accurate time constant can be realized. For ex-
ample, with CFLT = 10 nF, the –3 dB corner frequency is
3.2 kHz. Such filtering is useful in minimizing the output noise,
particularly when IPD is small. Multipole filters are more effec-
tive in reducing noise, and are discussed below. A capacitor
between VSUM and ground is essential for minimizing the
noise on this node. When the bias voltage at either VPDB or
VREF is not needed these pins should be left unconnected.
Slope and Intercept Adjustments
The choice of slope and intercept depends on the application.
The versatility of the AD8304 permits optimal choices to be
made in two common situations. First, it allows an input current
range of less than the full 160 dB to use the available voltage span
at the output. Second, it allows this output voltage range to be
optimally positioned to fit the input capacity of a subsequent
ADC. In special applications, very high slopes, such as 1 V/dec,
allow small subranges of IPD to be covered at high sensitivity.
The slope can be lowered without limit by the addition of a
shunt resistor, RS, from VLOG to ground. Since the resistance
at this pin is trimmed to 5 k
, the accuracy of the modified
slope will depend on the external resistor. It is calculated using:
V
VR
Rk
Y
YS
S
=
+
'5
(15)
3
4
PDB
BIAS
VREF
10
2
12
VPDB
VSUM
INPT
VSUM
5
1
VNEG
~10k
ACOM
14
VPS2
PWDN
VPS1
VREF
7
VLOG
8
BFIN
9
BFNG
TEMPERATURE
COMPENSATION
5k
11
VOUT
0.5V
IPD
NC
R1
750
10nF
C1
1nF
13
RA
15k
RB
10k
CFLT
200mV/DEC
VP
VOUT
500mV/DEC
NC = NO CONNECT
Figure 3. Basic Connections (RA, RB, CFLT are
optional; R1 and C1 are the default values)
For example, using RS = 3 k
, the slope is lowered to 75 mV per
decade or 3.75 mV/dB. Table I provides a selection of suitable
values for RS and the resulting slopes.
Table I. Examples of Lowering the Slope
RS (k )VY (mV/dec)
375
5
100
15
150
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