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參數(shù)資料
| 型號： | AD8304ARUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC LOGARITHM CONV 160DB 14-TSSOP |
| 設(shè)計資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準包裝： | 1,000 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. A
AD8304
–15–
Summing Node at Ground and Voltage Inputs
A negative supply may be used to reposition the input node at
ground potential. A voltage as small as –0.5 V is sufficient. Figure 13
shows the use of this feature. An input current of up to 10 mA is
supported.
This connection mode will be useful in cases where the source is a
positive voltage VSIG referenced to ground, rather than for use with
photodiodes, or other “perfect” current sources. RIN scales the
input current and should be chosen to optimally position the range
of IPD, or provide a very high input resistance, thus minimizing
the loading of the signal source. For example, assume a voltage
source that spans the four-decade range from 100 mV to 1 kV and
is desired to maximize RIN. When set to 1 G
, IPD spans the range
100 pA to 1 mA. Using a value of 10 M
, the same four decades
of input voltage would span the central current range of 10 nA
to 100 mA.
Smaller input voltages can be measured accurately when aided by
a small offset-nulling voltage applied to VSUM. The optional
network shown in Figure 13 provides more than
±20 mV for
this purpose.
6
3
4
PDB
BIAS
VREF
10
2
12
VPDB
VSUM
INPT
VSUM
5
1
VNEG
~10k
ACOM
14
VPS2
PWDN
VPS1
VREF
7
VLOG
8
BFIN
9
BFNG
TEMPERATURE
COMPENSATION
5k
11
VOUT
0.5V
NC
13
VP
NC = NO CONNECT
RB
RA
VOUT
RIN
VSIG
1k
10k
VP
VN
VLOW
IPD
AD8304
Figure 13. Using a Negative Supply and Placing VSUM at
Ground Permits Voltage-Mode Inputs
The minimum voltage that can be accurately measured is then
limited only by the drift in the input offset of the AD8304. The
specifications show the maximum spread over the full tempera-
ture and supply range. Over a limited temperature range, and with
a regulated supply, the offset drift will be lower; in this situation,
processing of inputs down to 5 mV is practicable.
The input system of the AD8304 is quasi-differential, so VSUM
can be placed at an arbitrary reference level VLOW, over a wide
range, and used as the “signal LO” of the source. For example,
using VP = 5 V and VN = –3 V, VLOW can be any voltage within
a
±2.5 V range.
Providing Negative Outputs and Rescaling
As noted, the AD8304 allows the buffer to drive a load to negative
voltages with respect to ACOM, the analog common pin, which
is grounded. A negative supply capable of supporting the input
current IPD must be used, the fraction of quiescent bias that flows
out of the VNEG Pin, and the load current at VLOG. For the
example shown in Figure 14, this totals less than 20 mA when
driving a 1 k
load as far as –4V.
The use of a much larger value for the intercept may be useful in
certain situations. In this example, it has been moved up four
decades, from the default value of 100 pA to the center of the full
eight-decade range at 1 mA. Using a voltage input as described
above, this corresponds to an altered voltage-mode intercept, VZ,
which would be 1 V for RIN = 1 M
. To take full advantage of the
larger output swing, the gain of the buffer has been increased to
4.53, resulting in a scaling of 900 mV/decade and a full-scale
output of
±3.6 V.
6
3
4
PDB
BIAS
VREF
10
2
12
VPDB
VSUM
INPT
VSUM
5
1
VNEG
~10k
ACOM
14
VPS2
PWDN
VPS1
VREF
7
VLOG
8
BFIN
9
BFNG
TEMPERATURE
COMPENSATION
5k
11
VOUT
0.5V
NC
13
VP
NC = NO CONNECT
RB
22.6k
RA
13.3k
VOUT
RIN
VSIG
1k
10k
VP
VN
VLOW
IPD
RL
1k
RC
12.4k
AD8304
Figure 14. Using a Negative Supply to Allow the
Output to Swing Below Ground
Inverting the Slope
The buffer is essentially an uncommitted op amp that can be used
to support the operation of the AD8304 in a variety of ways. It
can be completely disconnected from the signal chain when not
needed. Figure 15 shows its use as an inverting amplifier; this
changes the polarity of the slope. The output can either be
repositioned to all positive values by applying a fraction of VREF
to the BFIN Pin, or range negative when using a negative supply.
The full design for a practical application is left undefined in this
brief illustration, but a few cases will be discussed.
For example, suppose we need a slope of –30 mV/dB; this requires
the gain to be three. Since VLOG exhibits a source resistance of
5k
, RB must be 15 k. In cases where a small negative supply
is available, the output voltage can swing below ground, and the
BFIN Pin may be grounded. But a negative slope is still possible
when only a single supply is used; a positive offset, VOFS, is applied
to this pin, as indicated in Figure 15. In general, the resulting
output voltage can be expressed as:
V
R
k
V
I
V
OUT
B
Y
PD
Z
OFS
=
×
+
–
log
5
10
(16)
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