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參數(shù)資料
| 型號： | AD8324JRQZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRIVER CBL 3.3V 20QSOP |
| 標準包裝： | 1 |
| 類型： | 線路驅動器，發(fā)射器 |
| 應用： | 調(diào)制解調(diào)器，CATV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 20-QSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | AD8324JRQZ-REEL7DKR |
AD8324
Data Sheet
Rev. B | Page 12 of 16
APPLICATIONS INFORMATION
GENERAL APPLICATIONS
The AD8324 is primarily intended for use as the upstream power
amplifier (PA) in Data-Over-Cable Service Interface Specification
(DOCSIS) certified cable modems and CATV set-top boxes. The
upstream signal is either a quadrature phase shift keying (QPSK) or
a quadrature amplitude modulation (QAM) signal generated by a
digital signal processor (DSP), a dedicated QPSK/QAM modulator,
or a digital-to-analog converter (DAC). In all cases, the signal
must be low-pass filtered before it is applied to the PA in order
to filter out-of-band noise and higher order harmonics from the
amplified signal.
Due to the varying distances between the cable modem and the
headend, the upstream PA must be capable of varying the output
power by applying gain or attenuation. The ability to vary the
output power of the AD8324 ensures that the signal from the
cable modem has the proper level when it arrives at the headend.
The upstream signal path commonly includes a diplexer and
cable splitters. The AD8324 is designed to overcome losses
associated with these passive components in the upstream
cable path.
CIRCUIT DESCRIPTION
The AD8324 is composed of three analog functions in the transmit
enable mode. The input amplifier (preamp) can be used in a single-
ended or differential configuration. If the input is used in the
differential configuration, ensure that the input signals are 180°
out of phase and of equal amplitude. A vernier is used in the input
stage for controlling the fine 1 dB gain steps. This stage then drives
a DAC that provides the bulk of the attenuation for the AD8324.
The signals in the preamp and DAC blocks are differential to
improve the power supply rejection ratio (PSRR) and linearity.
A differential current is fed from the DAC into the output stage.
The output stage maintains 75 differential output impedance
in all power modes.
GAIN PROGRAMMING FOR THE AD8324
The AD8324 features a serial peripheral interface (SPI) for
programming the gain code settings. The SPI interface consists
of three digital data lines: CLK, DATEN, and SDATA. The DATEN
pin must be held low while the AD8324 is being programmed.
The SDATA pin accepts the serial data stream for programming
the AD8324 gain code. The CLK pin accepts the clock signal to
latch in the data from the SDATA line.
The AD8324 uses a 6-bit shift register for clocking in the data.
The shift register is designed to be programmed MSB first. The
timing interface for programming the AD8324 can be seen in
is held low, the serial bits on the SDATA line are shifted into
the register on the rising edge of the CLK pin.
For existing software that uses eight bits to program the cable
driver, the two MSBs are ignored. This allows the AD8324 to
be compatible with some existing system designs.
The AD8324 recognizes Gain Code 1 through Gain Code 60 (all
gain codes are in decimal, unless otherwise noted). When the
AD8324 is programmed with Gain Code 61 to Gain Code 63, it
internally defaults to maximum gain (Gain Code 60). If the pro-
grammed gain code is above 63, the AD8324 recognizes the six
LSBs only. For example, Gain Code 75 (01001011 binary) is
interpreted as Gain Code 11 (001011 binary) because the
two MSBs are ignored.
The programming range of the AD8324 is from –25.5 dB (Gain
Code 1) to +33.5 dB (Gain Code 60). The 59 dB gain range is linear
with a 1 dB change in a 1 LSB change in gain code. Figure 15
illustrates the gain step size of the AD8324 vs. gain code. The
AD8324 is characterized with a differential input signal and a
TOKO 458PT-1457 1:1 transformer at the output.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The VIN+ and VIN– inputs have a dc bias level of VCC/2; therefore,
ac-couple the input signal as shown in the typical application circuit
(see Figure 23). The differential input impedance of the AD8324 is
approximately 1.1 k, and the single-ended input is 550 . The
high input impedance of the AD8324 allows flexibility in termi-
nation and properly matching filter networks. The AD8324 exhibits
optimum performance when driven with a pure differential signal.
OUTPUT BIAS, IMPEDANCE, AND TERMINATION
The output stage of the AD8324 requires a bias of 3.3 V. Connect
the 3.3 V power supply to the center tap of the output transformer.
In addition, decouple the VCC that is applied to the center tap of
the transformer as shown in the typical application circuit (see
The output impedance of the AD8324 is 75 , regardless of
whether the amplifier is in transmit enable, transmit disable, or
sleep mode. When combined with a 1:1 voltage ratio transformer,
this eliminates the need for external back termination resistors. If
the output signal is evaluated using standard 50 test equipment,
use a minimum loss 75 to 50 pad to provide the test circuit
with the proper impedance match. When using a matching atten-
uator, note that there is 5.7 dB of power loss (7.5 dB voltage)
through the network.
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