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參數資料
| 型號： | AD8324JRQZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRIVER CBL 3.3V 20QSOP |
| 標準包裝： | 1 |
| 類型： | 線路驅動器，發(fā)射器 |
| 應用： | 調制解調器，CATV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 20-QSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | AD8324JRQZ-REEL7DKR |
Data Sheet
AD8324
Rev. B | Page 13 of 16
Figure 23. Typical Application Circuit
Table 7. Adjacent Channel Power
Adjacent Channel Symbol Rate (kSym/s)
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
160
–63
–64
–68
–71
–72
–66
320
–63
–64
–66
–70
–72
–67
640
–64
–65
–67
–71
–67
1280
–67
–65
–66
–68
–67
2560
–70
–67
–66
–67
–65
5120
–72
–70
–67
–64
POWER SUPPLY
Deliver the 3.3 V supply to each of the VCC pins via a low imped-
ance power bus. This ensures that each pin is at the same potential.
Decouple the power bus to ground using a 10 F tantalum
capacitor located close to the AD8324. In addition to the 10 F
capacitor, decouple the VCC pins to ground with ceramic chip
capacitors located close to the pins. In addition, decouple the
bypass pin (BYP). The printed circuit board (PCB) must have a
low impedance ground plane covering all unused portions of
the board, except in areas of the board where input and output
traces are in close proximity to the AD8324 and the output
transformer. Connect all AD8324 ground pins to the ground
plane to ensure proper grounding of all internal nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to PCB layout details prevents problems due
to board parasitics. Proper radio frequency (RF) design techniques
are mandatory. Keep the differential input and output traces as
short as possible. Keeping the traces short minimizes parasitic
capacitance and inductance, which is most critical between the
outputs of the AD8324 and the 1:1 output transformer. It is also
critical that all differential signal paths be symmetrical in length
and width.
In addition, the input and output traces must be adequately spaced
to minimize coupling (crosstalk) through the board. Following
these guidelines optimizes the overall performance of the AD8324
in all applications.
INITIAL POWER-UP
When the supply voltage is first applied to the AD8324, the gain
of the amplifier is initially set to Gain Code 1. As power is first
applied to the amplifier, hold the TXEN pin low (Logic 0) to pre-
vent forward signal transmission. After power is applied to the
amplifier, the gain can be set to the desired level by following the
procedure provided in the Gain Programming for the AD8324
section. The TXEN pin can then be brought from Logic 0 to
Logic 1, enabling forward signal transmission at the desired
gain level.
RAMP PIN AND BYP PIN FEATURES
The RAMP pin (Pin 15/Pin 17) is used to control the length of
the burst on and off transients. By default, leaving the RAMP
pin unconnected results in a transient that is fully compliant
with DOCSIS 2.0 Radio Frequency Interface (RFI) Specification,
Section 6.2.21.2, Spurious Emissions During Burst On/Off
Transients. DOCSIS requires that all between burst transients
be dissipated no faster than 2 s. Adding capacitance to the
RAMP pin slows the dissipation even more.
CLK
SDATA
DATEN
TXEN
GND
VCC
ZIN = 150
VCC
GND
DATEN
SDATA
CLK
GND
TXEN
RAMP
BYP
SLEEP
NC
GND
AD8324-JRQ
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1k
174
1k
1k
1k
1k
SLEEP
TO DIPLEXER
ZIN = 75
TOKO 458PT-1556
VIN+
VIN–
VIN+
VIN–
VOUT+
VOUT–
10
F
0.1
F
0.1
F
1:1
0.1
F
0.1
F
04339-0-023
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