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參數(shù)資料
| 型號： | AD8324JRQZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRIVER CBL 3.3V 20QSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路驅(qū)動器，發(fā)射器 |
| 應(yīng)用： | 調(diào)制解調(diào)器，CATV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-QSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD8324JRQZ-REEL7DKR |
AD8324
Data Sheet
Rev. B | Page 14 of 16
The BYP pin (Pin 12/Pin 14) is used to decouple the output stage
to ground. Typically, for normal DOCSIS operation, decouple
the BYP pin to ground with a 0.1 F capacitor. In applications
that require transient on/off times faster than 2 s, smaller
capacitors can be used; however, note that the BYP pin must
always be decoupled to ground.
POWER SAVING FEATURES
The AD8324 incorporates three distinct methods of reducing
power consumption: transmit disable and sleep modes for
between burst and shutdown modes, and gain dependent
quiescent current for transmit enable mode.
The asynchronous TXEN pin is used to place the AD8324 into
between burst mode. In this reduced current state, the 75 output
impedance is maintained. Applying Logic 0 to the TXEN pin
deactivates the on-chip amplifier, providing a 98.8% reduction
in consumed power. For 3.3 V operation, the supply current is
typically reduced from 207 mA to 2.5 mA. In this mode of
operation, between burst noise is minimized and high input to
output isolation is achieved. In addition to the TXEN pin, the
AD8324 also incorporates an asynchronous SLEEP pin that can
be used to further reduce the supply current to approximately
30 A. Applying Logic 0 to the SLEEP pin places the amplifier
into SLEEP mode. Transitioning into or out of SLEEP mode
results in a transient voltage at the output of the amplifier.
In addition to the sleep and transmit disable functions, the
AD8324 provides yet another means of reducing system power
consumption. While in the transmit enable state, the AD8324
incorporates supply current scaling that allows for lower power
consumption at lower gain codes. Figure 20 shows the typical
relationship between supply current and gain code.
DISTORTION, ADJACENT CHANNEL POWER,
AND DOCSIS
To deliver the DOCSIS specification required 58 dBmV of QPSK
signal and 55 dBmV of 16 QAM signal, the PA is required to
deliver up to 61 dBmV. This added power is required to comp-
ensate for losses associated with the diplex filter or other passive
components that may be included in the upstream path of cable
modems or set-top boxes. Note that the AD8324 is characterized
with a differential input signal. Figure 7 and Figure 10 show the
AD8324 second and third harmonic distortion performance vs.
the fundamental frequency for various output power levels.
These figures are useful for determining the in-band harmonic
levels from 5 MHz to 65 MHz. Harmonics higher in frequency
(more than 42 MHz for DOCSIS 2.0 specifications and more
than 65 MHz for EuroDOCSIS specifications) are sharply
attenuated by the low-pass filter function of the diplexer.
Another measure of signal integrity is adjacent channel power
(ACP). DOCSIS 2.0 RFI Specification, Section 6.2.21.1.1, states,
“Spurious emissions from a transmitted carrier may occur in an
adjacent channel that could be occupied by a carrier of the same
or different modulation rate.” Figure 13 shows the typical ACP for
a 61 dBmV (approximately 12 dBm) QPSK signal taken at the
output of the AD8324 during product characterization. The
transmit channel width and adjacent channel width in Figure 13
correspond to the symbol rates of 160 kSym/s. Table 7 shows the
ACP results for the AD8324 driving a QPSK, 61 dBmV signal for
all conditions in DOCSIS RFI Specification, Table 6-10, Adjacent
Channel Spurious Emissions Relative to the Transmitted Burst
Power Level.
UTILIZING DIPLEX FILTERS
The AD8324 is designed to drive 61 dBmV without any external
filtering and still meet DOCSIS spurious emissions and distortion
requirements. However, in most upstream CATV applications, a
diplex filter is used to separate the upstream and downstream
signal paths from one another. The diplex filter does have insertion
loss that the upstream driver needs to overcome, but it also
provides a low-pass filter. The addition of this low-pass filter to
the signal chain greatly attenuates second harmonic products of
channels more than 21 MHz and third harmonic products of
channels at or more than 14 MHz up for diplexers with a 42 MHz
upstream cutoff. Similar performance gains can be achieved
using European-specified diplexers to filter second harmonics
for channels more than 33 MHz and third harmonics for channels
more than 22 MHz (65 MHz upstream cutoff). This filtering
allows the AD8324 to drive up to 63 dBmV of QPSK (this level
varies by application and modulation type).
NOISE AND DOCSIS
At minimum gain, the AD8324 output noise spectral density is
1.3 nV/√Hz measured at 10 MHz. DOCSIS 2.0 RFI Specification
Table 6-11, Spurious Emissions in 5 to 42 MHz Relative to the
Transmitted Burst Power Level, specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 kSym/s is
20 × log [√(1.3 nV/√Hz)2 × 160 kHz] + 60 = –65.7 dBmV
Comparing the computed noise power of –65.7 dBmV to the
+8 dBmV signal yields –73.7 dBc, which meets the required
level set forth in DOCSIS 2.0 RFI Specification Table 6-11. As
the AD8324 gain is increased above this minimum value, the
output signal increases at a faster rate than the noise, resulting in
a signal-to-noise ratio that improves with gain. In transmit
disable mode, the output noise spectral density is 1.1 nV/√Hz,
which results in –67 dBmV when computed over 160 kSym/s.
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