VS = 5 V, T
參數(shù)資料
型號： AD8330ARQZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 23/32頁
文件大?。?/td> 0K
描述： IC AMP VGA 150MHZ LN LP 16QSOP
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 可變增益
電路數(shù)： 1
輸出類型： 差分，滿擺幅
轉(zhuǎn)換速率： 1500 V/µs
-3db帶寬： 150MHz
電流 - 輸入偏壓： 100nA
電流 - 電源： 20mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
配用： AD8330-EVALZ-ND - BOARD EVAL FOR AD8330
Data Sheet
AD8330
Rev. F | Page 3 of 32
SPECIFICATIONS
VS = 5 V, TA = 25°C, CL = 12 pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = Pin VMAG open circuit (0.5 V),
VOFST = 0 V, differential operation, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
INPUT INTERFACE
Pin INHI, Pin INLO
Full-Scale Input
V
DBS = 0 V, differential drive
±1.4
±2
V
DBS = 1.5 V
±4.5
±6.3
mV
Input Resistance
Pin-to-pin
800
1 k
1.2 k
Ω
Input Capacitance
Either pin to COMM
4
pF
Voltage Noise Spectral Density
f = 1 MHz, V
DBS = 1.5 V; inputs ac-shorted
5
nV/√Hz
Common-Mode Voltage Level
3.0
V
Input Offset
Pin OFST connected to Pin COMM
1
mV rms
Drift
2
μV/°C
Permissible CM Range1
0
V
S
V
Common-Mode AC Rejection
f = 1 MHz, 0.1 V rms
60
dB
f = 50 MHz
55
dB
OUTPUT INTERFACE
Pin OPHI, Pin OPLO
Small Signal –3 dB Bandwidth
0 V < V
DBS < 1.5 V
150
MHz
Peak Slew Rate
V
DBS = 0 V
1500
V/μs
Peak-to-Peak Output Swing
±1.8
±2
±2.2
V
MAG ≥ 2 V (peaks are supply limited)
±4
±4.5
V
Common-Mode Voltage
Pin CNTR O/C
2.4
2.5
2.6
V
Voltage Noise Spectral Density
f = 1 MHz, V
DBS = 0 V
62
nV/√Hz
Differential Output Impedance
Pin-to-pin
120
150
180
Ω
V
OUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ
62
dBc
V
OUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ
53
dBc
OUTPUT OFFSET CONTROL
Pin OFST
AC-Coupled Offset
C
HPF on Pin OFST (0 V < VDBS < 1.5 V)
10
mV rms
High-Pass Corner Frequency
C
HPF = 3.3 nF, from OFST to CNTR (scales as 1/CHPF)
100
kHz
COMMON-MODE CONTROL
Pin CNTR
Usable Voltage Range
0.5
4.5
V
Input Resistance
From Pin CNTR to V
S/2
4
kΩ
DECIBEL GAIN CONTROL
VDBS, CMGN, and MODE pins
Normal Voltage Range
CMGN connected to COMM
0 to 1.5
V
Elevated Range
CMGN O/C (V
CMGN rises to 0.2 V)
0.2 to 1.7
V
Gain Scaling
Mode high or low
27
30
33
mV/dB
Gain Linearity Error
0.3 V ≤ V
DBS ≤ 1.2 V
0.35
±0.1
+0.35
dB
Absolute Gain Error
V
DBS = 0 V
2
±0.5
+2
dB
Bias Current
Flows out of Pin VDBS
100
nA
Incremental Resistance
100
MΩ
Gain Settling Time to 0.5 dB Error
V
DBS stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V
250
ns
Mode Up/Down
Pin MODE
Mode Up Logic Level
Gain increases with V
DBS, MODE = O/C
1.5
V
Mode Down Logic Level
Gain decreases with V
DBS
0.5
V
LINEAR GAIN INTERFACE
Pin VMAG, Pin CMGN
Peak Output Scaling, Gain vs. V
MAG
3.8
4.0
4.2
V/V
Gain Multiplication Factor vs. V
MAG
Gain is nominal when V
MAG = 0.5 V
×2
Usable Input Range
0
5
V
Default Voltage
V
MAG O/C
0.48
0.5
0.52
V
Incremental Resistance
4
kΩ
Bandwidth
For V
MAG ≥ 0.1 V
150
MHz
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